MU9C8148 データシートの表示（PDF） - Music Semiconductors
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MU9C8148 Datasheet PDF : 24 Pages
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MU9C8148
PINOUT DIAGRAMS
NC
NC
NC
A4
A3
A2
A1
A0
/INT
/FULL,/EMPTY
/INTEL
/RESET
/EC
/CM
/FI
/MI
/E
/W
GND
VCC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
61
40
62
39
63
38
64
37
65
36
66
35
67
34
68
33
69
32
70
MU9C8148
31
71
80-pin TQFP
30
72
29
73
28
74
27
75
26
76
25
77
24
78
23
79
22
80
21
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
GND
D11
D10 44
D12
D9 45
D13
D14
D15
/HBRDY
/HBEN
/HBDIR
/RQ
D8 46
D7 47
D6 48
D5 49
D4 50
D3 51
/RQI
D2 52
XFAIL,/FLUSH
D1 53
XMATCH
/RDY
RXD
RXC
VCC
NC
NC
D0 54
/WS, /UDS 55
/RS, /LDS 56
/CS 57
ALE, SRNW 58
GND 59
GND
VCC 60
MU9C8148
68-pin PLCC
26 GND
25 DQ0
24 DQ1
23 DQ2
22 DQ3
21 DQ4
20 DQ5
19 DQ6
18 DQ7
17 DQ8
16 DQ9
15 DQ10
14 DQ11
13 DQ12
12 DQ13
11 DQ14
10 DQ15
LANCAM Interface:
PIN DESCRIPTIONS
(/X indicates an active LOW function)
/EC (Enable Comparison, Output, Three-state TTL)
DQ15–DQ0 (Data Bus, Input/Output, TTL)
The DQ15–DQ0 lines transfer data, commands and status
between the MU9C8148 and the LANCAM. The direction and
nature of the information that flows between the devices is
determined by the states of /CM and /W.
/E (Chip Enable, Output, Three-state TTL)
The /E output enables the LANCAM while LOW and registers
/W, /CM, /EC and DQ15–DQ0 (if /W is LOW) on the falling
edge of /E. If /W is HIGH, data on DQ15–DQ0 from the
LANCAM is valid on the rising edge of /E.
/W (Write Enable, Output, Three-state TTL)
The /W output selects the direction of data flow during a
LANCAM cycle. DQ15–DQ0 write to the LANCAM if /W is LOW
at the falling edge of /E. Read data is output from the LANCAM
to DQ15–DQ0 on the rising edge of /E if /W is HIGH at the
falling edge of /E.
The /EC signal enables the LANCAM /MF pin to output the
results of a comparison. If /EC is LOW at the falling edge of /E
for a given cycle, the LANCAM /MF output is enabled on the
rising edge of /E. If /EC is HIGH, the LANCAM /MF output is
held HIGH.
/MI (Match Flag, Input, TTL)
The LANCAM /MF pin takes the MU9C8148's /MI input LOW if
a valid match occurs during a Comparison cycle, and /EC was
also LOW at the start of that cycle. The state of the /MI pin
controls branching in the MU9C8148's routines.
/FI (Full Flag, Input, TTL)
The /FI input will be driven LOW by the LANCAM /FF output pin
if all the LANCAM memory locations have valid contents. The
status of the /FI pin can be read by the Host processor from the
MU9C8148's Control register.
Transceiver Interface:
/CM (Data/Command Select, Output, Three-state
TTL)
The /CM signal determines whether DQ15–DQ0 contain
LANCAM data or commands. /CM is LOW at the falling edge
of /E for Command cycles and HIGH for Data cycles.
RXD (Receive Data, Input, TTL)
The RXD pin monitors the data received by the TMS38053/4
from the Token Ring. RXD is clocked on the rising edge of
RXC.
Rev. 5.5 Draft web
2
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