MX29F8100 データシートの表示（PDF） - Macronix International

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MX29F8100

8M-BIT [1M x 8/512K x 16] CMOS SINGLE VOLTAGE FLASH MEMORY

Macronix International 

INDEX

MX29F8100

CHIP ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command-80H. Two more "unlock" write cycles

are then followed by the chip erase command-10H.

Chip erase does not require the user to program the

device prior to erase.

The automatic erase begins on the rising edge of the last

WE pulse in the command sequence and terminates

when the status on DQ7 is "1" at which time the device

stays at read status register mode. The device remains

enabled for read status register mode until the CIR

contents are altered by a valid command

sequence.(Refer to table 3,6 and Figure 2,7,9)

Table 5. MX29F8100 Sector Address Table

(Byte-Wide Mode)

A19 A18 A17 A16 Address Range[A18, -1]

SA0 X 0 0 0

00000H--1FFFFH

SA1 X 0 0 1

20000H--3FFFFH

SA2 X 0 1 0

40000H--5FFFFH

SA3 X 0 1 1

60000H--7FFFFH

SA4 X 1 0 0

80000H--9FFFFH

1 ... ... ...

................

SA17 X 1 1 1

E0000H--FFFFFH

SECTOR ERASE

Sector erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

set-up command-80H. Two more "unlock" write cycles

are then followed by the sector erase command-30H.

The sector address is latched on the falling edge of WE,

while the command (data) is latched on the rising edge of

WE.

Sector erase does not require the user to program the

device prior to erase. The system is not required to

provide any controls or timings during these operations.

The automatic sector erase begins on the rising edge of

the last WE pulse in the command sequence and

terminates when the status on DQ7 is "1" at which time

the device stays at read status register mode. The device

remains enabled for read status register mode until the

CIR contents are altered by a valid command

sequence.(Refer to table 3,6 and Figure 3,4,7,9))

ERASE SUSPEND

This command only has meaning while the the WSM is

executing SECTOR or CHIP erase operation, and

therefore will only be responded to during SECTOR or

CHIP erase operation. After this command has been

executed, the CIR will initiate the WSM to suspend erase

operations, and then return to Read Status Register

mode. The WSM will set the DQ6 bit to a "1". Once the

WSM has reached the Suspend state,the WSM will set

the DQ7 bit to a "1", At this time, WSM allows the CIR to

respond to the Read Array, Read Status Register, Abort

and Erase Resume commands only. In this mode, the

CIR will not resopnd to any other comands. The WSM will

continue to run, idling in the SUSPEND state, regardless

of the state of all input control pins, with the exclusion of

PWD. PWD low will immediately shut down the WSM and

the remainder of the chip.

ERASE RESUME

This command will cause the CIR to clear the suspend

state and set the DQ6 to a '0', but only if an Erase

Suspend command was previously issued. Erase

Resume will not have any effect in all other conditions.

P/N: PM0262

REV. 2.0, JAN. 22, 1999

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