NT3980 データシートの表示（PDF） - Unspecified
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NT3980 Datasheet PDF : 13 Pages
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NT3980
TFT LCD Source Driver
Absolute Maximum Ratings*
*Comments
Supply voltage, Vcc
Supply voltage, AVDD
Input voltage, V1~ V10
Input range(digital inputs)
Storage temperature
Operating temperature
-0.3V to 5V
-0.3V to +12V
-0.3 to AVDD+0.3
-0.3 to Vcc+0.3
-55℃ to 110℃
-30℃ to 75℃
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or under any other conditions above those
indicated in the operational sections of this specification are
not implied and exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
DC Electrical Characteristics (Vcc =3.3V , AV DD=10V, AVSS=GND=0V, TA= -30℃~ 75℃)
(For the digital circuit)
Parameter
Symbol Min. Typ.
Supply Voltage
Vcc
2.5
--
Low Level Input Voltage
Vil
0
-
High Level Input Voltage
Vih 0.7xVcc -
High Level Output Voltage
Voh 0.7xVcc -
Low Level Output Voltage
Vol
--
-
Input Leakage Current
Ii
-1
-
Gamma correction Current
Iref
--
800
Digital Operating Current
Icc
-
3
Max. Unit
Conditions
3.6
V Digital power
0.3xVcc V For the digital circuit
Vcc
V For the digital circuit
--
V DIO1(O), DIO2(O), Ioh=-0.4mA
0.3Vcc V DIO1(O), DIO2(O), Iol=0.4mA
1
µA For LD,CLK,SHL,Dxx,POL,REV1/2,DIO1/2
1000
6
µA For V1-V5=4.75V or V6-V10=4.75V
mA Vcc=3.6V, AVDD=9.5V,fld=50kHz,fclk=45MHz
No load
(For the analog circuit)
Parameter
Supply Voltage
Input level of V1 ~ V5
Input level of V6 ~ V10
Output Voltage Deviation
Average output voltage
dispersion
Dynamic Range of Output
Low-Level Output Current
High-Level Output Current
Analog Operating Current
Symbol
AVDD
Vref
Vref
Vvd
Vod
Vdr
IOL
IOH
IDD
Min.
7.0
AVDD/2
0.1
--
--
--
0.1
-150
150
-
Input capacitance1
Input capacitance2
C1
--
C2
--
Typ.
--
-
±6
±2
±5
-
-300
300
6
5
10
Max. Unit
10
V
AVDD-0.1 V
AVDD/2 V
±12
mV
±5
mV
±10
mV
Conditions
For the analog circuit power
Gamma correction voltage
Gamma correction voltage
Input data ‘without’ offset cancellation
Input data ‘with’ offset cancellation (Note1)
OUT1 ~ OUT384,input data 00 to FF.
AVDD-0.1 V OUT1 ~ OUT384
-
µA OUT1 ~ OUT384; Vo=0.1V V.S 1.0V
-
µA OUT1 ~ OUT384; Vo=9.9V V.S 9V
12
mA Vcc=3.6V,AVDD=9.5V,fld=50kHz,fclk=45MHz
No load
10
pF For Input pins ,except DIO1,DIO2
15
pF For DIO1,DIO2
(Note 1) This chip needs 253 CLK cycles to use its 'offset cancellation' function to get a precision output voltage.
Please refer to the timing chart below :
LD
CLK
1
2
3
4
5
252 253 254
Outputs
Finish 'offset
cancellation'
Version 1.0
10
October 16, 2001
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