PHD101NQ03LT データシートの表示（PDF） - NXP Semiconductors.
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PHD101NQ03LT Datasheet PDF : 13 Pages
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NXP Semiconductors
PHD101NQ03LT
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
VDS
VDGR
VGS
ID
IDM
Ptot
Tstg
Tj
VGSM
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
peak drain current
total power dissipation
storage temperature
junction temperature
peak gate-source
voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
Tj ≥ 25 °C; Tj ≤ 175 °C; RGS = 20 kΩ
VGS = 10 V; Tmb = 100 °C; see Figure 1
VGS = 10 V; Tmb = 25 °C; see Figure 1; see Figure 3
tp ≤ 10 µs; pulsed; Tmb = 25 °C; see Figure 3
Tmb = 25 °C; see Figure 2
pulsed; δ = 25 %; tp ≤ 50 µs
Source-drain diode
IS
source current
ISM
peak source current
Avalanche ruggedness
Tmb = 25 °C
tp ≤ 10 µs; pulsed; Tmb = 25 °C
EDS(AL)S
non-repetitive
VGS = 10 V; Tj(init) = 25 °C; ID = 43 A; Vsup ≤ 15 V;
drain-source avalanche unclamped; tp = 0.19 ms; RGS = 50 Ω
energy
Min Max Unit
-
30
V
-
30
V
-20 20
V
-
75
A
-
75
A
-
240 A
-
166 W
-55 175 °C
-55 175 °C
-25 25
V
-
75
A
-
240 A
-
185 mJ
120
Ider
(%)
80
03ai19
120
Pder
(%)
80
03aa16
40
40
0
0
50
100
150
200
Tmb (°C)
0
0
50
100
150
200
Tmb (°C)
Fig 1. Normalized continuous drain current as a
function of mounting base temperature
Fig 2. Normalized total power dissipation as a
function of mounting base temperature
PHD101NQ03LT_4
Product data sheet
Rev. 04 — 9 June 2009
© NXP B.V. 2009. All rights reserved.
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