PM6685(2005) データシートの表示（PDF） - STMicroelectronics

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PM6685
(Rev.:2005)

DUAL STEP-DOWN CONTROLLER WITH AUXILARY VOLTAGES FOR NOTEBOOK SYSTEM POWER

STMicroelectronics 

3 Block & pin connection diagrams

PM6685

Table 3. Pin description

Pin No

PM6685

Function

1

SGND

Signal ground. Reference for internal logic circuitry.

2

COMP3 DC voltage error compensation pin for the 3.3V switching section.

Frequency selection pin. It provides a selectable switching frequency, allowing

3

FSEL

either 200kHz/300kHz, 300kHz/400kHz or 400kHz/500kz operation of the 5V/

3.3V switching sections.

3.3V SMPS enable input. The 3.3V section is enabled appling a high logic level

(>2.4V) to this pin, while is disabled appling a low logic level (<0.8V). When the

4

EN3

section is disabled the High Side gate driver goes low and Low Side gate driver

goes high. If both EN3 and EN5 pins are low and SHDN pin is high the device

enters in standby mode.

Shutdown control input. The device enters its shutdown mode with 9µA of supply

current if VSHDN is less than the device off threshold voltage and doesn't restart

5

SHDN

until VSHDN is greater than the device on threshold voltage. The SHDN pin can

be connected to Vbatt through a voltage divider to program an undervoltage

lockout. In shutdown mode, the gate drivers of the two switching sections are in

high impedance.

Power Good ouput signal for the 3.3V linear regulator. This pin is an open drain

6

PGOOD LDO3 output. It is shorted to GND if LDO3_SEL pin is at its low level or if the ouput

voltage on LDO3 pin is lower than 2.6V.

3.3V Linear regulator output. LDO3 can provide 100mA peak current. If

LDO3_SEL pin is connected to VREF and OUT3 is greater than the LDO3

bootstrap switch threshold, the LDO3 regulator shuts down and the LDO3 pin will

7

LDO3

be directly connected to OUT3 through a 3 (max) switch.

If LDO3_SEL pin is at its low level the LDO3 is always OFF.

If LDO3_SEL pin is at its high level the LDO3 is always ON.

8

OUT3

Output voltage sense for the 3.3V switching section.This pin must be directly

connected to the output voltage of the switching section.

9

BOOT3

Bootstrap capacitor connection for the switching 3.3V section. It supplies the high-

side gate driver.

10

HGATE3 High-side gate driver ouput for the 3.3V section.

11

PHASE3

Switch node connection and return path for the high side driver for the 3.3V

section.

Current sense input for the switching 3.3V section. This pin must be connected

12

CSENSE3

through a resistor to the drain of the synchronous rectifier (RDSON sensing) or to

the source of the synchronous rectifier (RSENSE sensing) to set the current limit

threshold.

13

LGATE3 Low-side gate driver output for the 3.3V section.

14

PGND

Power ground.

15

LGATE5 Low-side gate driver output for the 5V section.

16

SGND2 Signal ground for analog circuitry.

Internal 5V regulator bypass connection. When the main 5V ouput voltage is

greater than the boostrap switch threshold, the LDO5 regulator shuts down and

17

V5SW

the LDO5 pin will be directly connected to OUT5 through a 3 (max) switch.

If not used, it must be tied to ground.

6/16

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