ML6697CQ データシートの表示（PDF） - Micro Linear Corporation

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ML6697CQ

100BASE-TX Physical Layer with MII

Micro Linear Corporation 

FUNCTIONAL DESCRIPTION

TRANSMIT SECTION

The transmitter includes everything necessary to accept

4-bit data nibbles clocked in at 25MHz at the MII and

output scrambled, 5-bit encoded MLT-3 signals into twisted

pair at 100Mbps. The on-chip transmit PLL converts a

25MHz TTL-level clock at TXCLKIN to an internal 125MHz

bit clock. TXCLK from the ML6697 clocks transmit data

from the MAC into the ML6697’s TXD<3:0> input pins

upon assertion of TXEN. Data from the TXD<3:0> inputs are

5-bit encoded, scrambled, and converted from parallel to

serial form at the 125MHz clock rate. The serial transmit

data is converted to MLT-3 3-level code and driven

differentially out of the TPOUTP and TPOUTN pins at

nominal ±2V levels with the proper loads. The transmitter is

designed to drive a center-tapped transformer with a 2:1

winding ratio, so a differential 400W load is used on the

transformer primary to properly terminate the 100W cable

and termination on the secondary. The transformer’s center

tap must be tied to VCC. A 2:1 transformer allows using a

±20mA output current. Using a 1:1 transformer would have

required twice the output current and increased the on-chip

power dissipation. An external 2.49kW, 1% resistor at the

RTSET pin creates the correct output levels at TPOUTP/N.

Driving TXER high when TXEN is high causes the H symbol

(00100) to appear in scrambled MLT-3 form at TPOUTP/N.

The media access controller asserts TXER synchronously

with TXCLK rising edge, and the H symbol appears at least

once in place of a valid symbol in the current packet.

With no data at TXD<3:0> scrambled idle appears at

TPOUTP/N.

ML6697

RECEIVE SECTION

The receiver includes all necessary functions for

converting 3-level MLT-3 signals from the twisted-pair

media to 4-bit data nibbles at RXD<3:0> with extracted

clock at RXCLK. The adaptive equalizer compensates for

cable distortion and attenuation, corrects for DC baseline

wander, and converts the MLT-3 signal to 2-level NRZ.

The receive PLL extracts clock from the equalized signal,

providing additional jitter attenuation, and clocks the

signal through the serial to parallel converter. The

resulting 5-bit nibbles are descrambled, aligned and

decoded, and appear at RXD<3:0>. The ML6692 asserts

RXDV when it’s ready to present properly decoded

receive data at RXD<3:0>. The extracted clock appears at

RXCLK. Resistor RGMSET sets internal time constants

controlling the adaptive equalizer’s transfer function.

RGMSET must be set to 9.53kW (1%).

The receiver will assert RXER high if it detects code errors

in the receive data packet, or if the idle symbols between

packets are corrupted.

CRS goes high whenever there is non-idle receive activity

in the network.

ML6697 PHY MANAGEMENT FUNCTIONS

The ML6697 has management functions controlled by the

register locations given in Tables 1 and 2. There are two

16-bit MII Management registers, with several unused

locations. Register 0 (Table 1) is the basic control register

(read/write). Register 1 (Table 2) is the basic status register

(read-only). The ML6697 powers on with all management

register bits set to their default values.

See IEEE 802.3u section 22.2.4 for a discussion of MII

management functions and status/control register

definitions.

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