ML6697CH データシートの表示（PDF） - Micro Linear Corporation

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ML6697CH

100BASE-TX Physical Layer with MII

Micro Linear Corporation 

ML6697

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

MDC-MDIO (MII Management Interface)

tSPWS

Write Setup Time, MDIO Data

Valid to MDC Rising Edge

1.4V Point

10

ns

tSPWH

Write Hold Time, MDIO Data

Valid After MDC Rising Edge

1.4V Point

10

ns

tSPRS

Read Setup Time, MDIO Data

Valid to MDC Rising Edge

1.4V Point

100

ns

tSPRH

Read Hold Time, MDIO Data

Valid After MDC Rising Edge

1.4V Point

0

ns

tCPER

Period of MDC

400

ns

tCPW

Pulsewidth of MDC

Positive or negative pulses

160

ns

Note 1.

Note 2.

Note 3.

Note 4.

Note 5.

Note 6.

Note 7.

Note 8.

Note 9.

Note 10.

Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.

Measured using the test circuit shown in fig. 1, under the following conditions:

RLP = 200W, RLS = 49.9W, RTSET = 2.49kW.

All resistors are 1% tolerance.

Output current amplitude is IOUT = 40 ´ 1.25V/RTSET.

Measured relative to ideal negative and positive signal 50% points, using the four successive MLT-3 transitions for the 01010101 bit sequence.

Time difference between 10% and 90% levels of the transition from the baseline voltage (nominally zero) to either the positive or negative peak signal voltage. The

times specified here correlate to the transition times defined in the ANSI X3T9.5 TP-PMD Rev 2.0 working draft, section 9.1.6, which include the effects of the

external network coupling transformer and EMI/RFI emissions filter.

Differential test load is shown in fig. 1 (see note 2).

Defined as the percentage excursion of the differential signal transition beyond its final adjusted value during the symbol interval following the transition. The

adjusted value is obtained by doing a straight line best-fit to an output waveform containing 14 bit-times of no transition preceded by a transition from zero to

either a positive or negative signal peak; the adjusted value is the point at which the straight line fit meets the rising or falling signal edge.

From first rising edge of TXCLK after TXEN goes high, to first bit of J at the MDI.

From first bit of J at the MDI, to CRS.

From first bit of J at the MDI, to first rising edge of RXCLK after RXDV goes high.

VCC

TPOUTP

RLP

200Ω

TPOUTN

RLP

200Ω

2:1

1

RLS

49.9Ω

2

RLS

49.9Ω

Figure 1.

9

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