ML6696CH データシートの表示（PDF） - Micro Linear Corporation

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ML6696CH

100BASE-X Fiber Physical Layer

Micro Linear Corporation 

ML6696

PIN DESCRIPTION (Pin Number in Parentheses is for PLCC Version) (Continued)

PIN NAME

FUNCTION

PIN NAME

FUNCTION

30 (32) CAPB

31, 32

(33) AGND4B

33 (34) VIN–

34 (35) VIN+

35, 36

(36, 37) AVCC4B

37 (38) LINK100

38 (39) AGND4A

39 (40) AVCC4A

40 (41) AVCC3B

41 (42) AVCC3A

42 (43) RTSET

43, 44

(44) AGND3

Data quantizer input bias bypass

capacitor input. The capacitor tied

between this pin and AVCC filters

the quantizer’s internal input bias

reference. A 0.1µF surface-mount

capacitor is recommended.

Analog ground

Receive quantizer negative input.

This input should be tied to

AVCCQ through an AC coupling

capacitor. (0.01µF recommended)

Receive quantizer positive input.

This input receives 100BASE-FX

signals from the network optical

receiver through an AC coupling

capacitor. (0.01µF recommended).

Analog positive power supply

100BASE-FX link activity open-

drain output. LINK100 pulls low

when there is 100BASE-FX activity

at VIN+/–. This output is capable

of sinking sufficient current to

directly drive a status LED in

series with a current limiting

resistor.

Analog ground

Analog positive power supply

Analog positive power supply

Analog positive power supply

Transmit level bias resistor. For

100BASE-FX, an external 2.32kW,

1% resistor connected between

RTSET and AGND3 sets a

precision constant bias current

that gives a nominal output "on"

current of 75mA at IOUT.

Analog ground

47, 48

(46) IOUT

49, 50,

51 (47) AGND2

52 (48) AVCC2

53 (49) EDOUT

54 (50) ECLK

55 (51) EDIN

56 (52) AVCC1

57 (1) CLKREF

Transmit LED output. This open-

collector current output drives

NRZI waveforms into a network

LED.

Analog ground

Analog positive power supply

Initialization Interface data out

CMOS input. With EDIN low at

power up, EDOUT has no

function. With EDIN floating at

power up, EDOUT is the serial

data input for configuration data

from an EEPROM. With EDIN high

at power up, EDOUT is the input

for configuration data from an

external microcontroller. (Table 1)

Initialization Interface clock

CMOS input/output. With EDIN

low at power up, ECLK is inactive.

With EDIN floating at power up,

ECLK is the ML6696’s clock

output for timing the configuration

data from an external EEPROM.

With EDIN high at power up,

ECLK is the clock input for timing

configuration data from an

external microcontroller. (Table 1)

Initialization Interface mode

select and EEPROM interface data

in CMOS input/output. EDIN

selects one of three possible

interface modes at power up. See

the Initialization Interface section

for more information. (Table 1)

Analog positive power supply

Transmit clock TTL input. This

25MHz clock is the frequency

reference for the internal TX PLL

clock synthesizer and logic. This

pin should be driven by an

external 25MHz clock at TTL

levels.

45, 46

(45) IOUT

Transmit LED output. This pin

connects through an external 15W

resistor to AVCC when the part is

used to drive a network LED.

58 (2) AGND1

59 (3) TXD3

Analog ground

Transmit data TTL input. TXD<3:0>

inputs accept TX data symbols from

the MII. Data appearing at TXD<3:0>

are clocked into the ML6696 on the

rising edge of TXCLK.

4

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