RMPA0913C-58 データシートの表示（PDF） - Unspecified

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RMPA0913C-58

3.5V AMPS/CDMA Power Amplifier

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R aytheon Commercial E lectronics

RMPA0913C-58

3.5V AMPS/CDMA Power Amplifier

Application Information for the RMPA0913C-58

CAUTION: THIS IS AN ESD SENSITIVE DEVICE.

The following describes a procedure for evaluating the Raytheon RMPA0913C-58, a monolithic high

efficiency power amplifier, in a surface mount package, designed for use in the AMPS/CDMA dual mode

portable phones. Figure 1 shows the package outline and pin designations. Figure 2 shows the functional

block diagram of the packaged product. It should be noted that the amplifier requires external

passive components for DC bias and RF input and output matching circuits. A recommended schematic

is shown in figure 3. The gate biases for the two stages of the amplifier are set by simple on-chip circuits.

Figure 4 shows a typical layout of an evaluation board (RMPA0913C-58-TB), corresponding

to the schematic circuit of figure 3. The following should be noted:

(1) Pin designations and their functions are as shown in figure 1 and Table 1.

(2) Vg1, Vg2 are denoted as the Gate Voltages (negative) applied at the pins of the package

(3) Vgg1, Vgg2 are denoted as the negative supply voltages at the evaluation board terminals

(4) Vd1, Vd2 are denoted as the Drain Voltages (positive) applied at the pins of the package

(5) Vdd1, Vdd2 are denoted as the positive supply voltages at the evaluation board terminals

Note: the two drain voltages are tied to the same terminal denoted as Vdd on the evaluation board

Test Procedure for the evaluation board (RMPA0913C-58-TB)

CAUTION:

LOSS OF GATE VOLTAGES (VG1, VG2) WHILE DRAIN VOLTAGES (VD1,VD2)

ARE PRESENT MAY DAMAGE THE AMPLIFIER.

The following sequence must be followed to properly test the amplifier:

Step 1: Turn off RF input power.

Step 2: Use GND terminal of the evaluation board for the ground of the DC supplies.

Slowly apply gate supply voltages of -3.0 V to the board terminals Vgg1, Vgg2

to pinch-off the two stages.

Step 3: Slowly apply drain supply voltage of +3.5 V to the board terminals Vdd.

Step 4:

Adjust the gate supply voltages Vgg1, Vgg2 to the values shown on the data summary

supplied with the sample. (First adjust Vgg2 to set Idq2. Then adjust Vgg1 to set Iddq=Idq1+Idq2.

These gate voltages need not be changed. However, Vgg1,Vgg2 may be adjusted only when

different quiescent bias currents are desired for performance trade-off evaluation).

Step 5: After the bias condition is established, RF input signal may now be applied at the

appropriate frequency band. Adjust RF input signal power level as required.

Step 6: Follow turn-off sequence of:

(i) Turn off RF Input Power (ii) Turn down and off drain voltage Vdd.

(iii) Turn down and off gate voltages Vgg1, Vgg2.

Raytheon reserves the right to update or change specifications without notice.

Tel: 978-684-8663

FAX: 978-684-5480

www.raytheon.com/micro

Revised March 30,2000

Page 3

Raytheon RF Components

362 Lowell Street

Andover, MA 01810

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