ML6695 データシートの表示（PDF） - Micro Linear Corporation

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ML6695

100BASE-X Fiber Physical Layer With 5-bit Interface

Micro Linear Corporation 

ML6695

PIN CONFIGURATION

ML6695

44-Pin PLCC (Q44)

PWRDN

RSM4

RSM3

DGND1

RSM2

DVCC1

RSM1

DGND2

RSM0

RXC

DGND3

6 5 4 3 2 1 44 43 42 41 40

7

39

8

38

9

37

10

36

11

35

12

34

13

33

14

32

15

31

16

30

17

29

18 19 20 21 22 23 24 25 26 27 28

IOUT

IOUT

AGND3

RTSET

AVCC3A

AVCC3B

AVCC4A

AGND4A

AVCC4B

VIN+

VIN–

TOP VIEW

PIN DESCRIPTION

PIN NAME

FUNCTION

1

AGND1

2

TSM4

Analog ground

Transmit data TTL inputs. TSM 0-4

inputs accept TX data symbols

from the MII. Data appearing at

TSM 0-4 are clocked into the

ML6695 on the rising edge of

TXCLK .

3

TSM3

Transmit data TTL inputs. TSM 0-4

inputs accept TX data symbols

from the MII. Data appearing at

TSM 0-4 are clocked into the

ML6695 on the rising edge of

TXC.

4

TSM2

Transmit data TTL inputs. TSM 0-4

inputs accept TX data symbols

from the MII. Data appearing at

TSM 0-4 are clocked into the

ML6695 on the rising edge of

TXC.

PIN NAME

5

TSM1

6

TSM0

7

PWRDN

8

RSM4

FUNCTION

Transmit data TTL inputs. TSM 0-4

inputs accept TX data symbols

from the MII. Data appearing at

TSM 0-4 are clocked into the

ML6695 on the rising edge of TXC.

Transmit data TTL inputs. TSM 0-4

inputs accept TX data symbols

from the MII. Data appearing at

TSM 0-4 are clocked into the

ML6695 on the rising edge of TXC.

Powerdown TTL input. Driving this

pin low, or floating the pin, powers

the ML6695 down to a low-

current, inoperative state. Driving

PWRDN high enables the

ML6695.

Receive data TTL outputs. RSM 0-

4 output may be sampled

synchronously with RXC’s rising

edge.

2

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