SAA7710T データシートの表示（PDF） - Philips Electronics
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SAA7710T Datasheet PDF : 28 Pages
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Philips Semiconductors
Dolby* Pro Logic Surround;
Incredible Sound
Product specification
SAA7710T
I2C-bus control and commands
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for 2-way, 2-line communication between
different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be
connected to the VDDX via a pull-up resistor when
connected to the output stages of a microprocessor.
Data transfer can only be initiated when the bus is not
busy.
BIT TRANSFER
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the
HIGH period of the clock pulse as changes in the data line
at this time will be interpreted as control signals.
The maximum clock frequency is 100 kHz (see Fig.7).
START AND STOP CONDITIONS
Both data and clock lines remain HIGH when the bus is not
busy. A HIGH-to-LOW transition of the data line, while the
clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock
is HIGH is defined as the STOP condition (P) (see Fig.8).
DATA TRANSFER
A device generating a message is a ‘transmitter’, a device
receiving a message is the ‘receiver’. The device that
controls the message is the ‘master’ and the devices which
are controlled by the master are the ‘slaves’ (see Fig.9).
ACKNOWLEDGE
The number of data bytes transferred between the START
and STOP conditions from transmitter to receiver is not
limited. Each byte of eight bits is followed by one
acknowledge bit. The acknowledge bit is a HIGH level put
on the bus by the transmitter whereas the master
generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an
acknowledge after the reception of each byte. Also a
master must generate an acknowledge after the reception
of each byte that has been clocked out of the slave
transmitter. The device that acknowledges has to pull
down the SDA line during the acknowledge clock pulse, so
that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse, set up and hold times
must be taken into account. A master receiver must signal
an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of
the slave. In this event the transmitter must leave the data
line HIGH to enable the master to generate a STOP
condition (see Fig.10).
handbook, full pagewidth
SDA
SCL
data line
stable
data valid
change
of data
allowed
MLC160
1998 Mar 13
Fig.7 Bit transfer on the I2C-bus.
10
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