SAA7710T データシートの表示（PDF） - Philips Electronics

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SAA7710T

Dolby* Pro Logic Surround; Incredible Sound

Philips Electronics 

Philips Semiconductors

Dolby* Pro Logic Surround;

Incredible Sound

I2S-bus Interfaces and system clock

I2S-BUS BASICS

handbook, full pagewidth

SCK

SD WS

Tcy

tLC≥0.35 T

tHC≥0.35 T

tsr≥0.2 T

thr≥0

VIH (70%)

VIL (20%)

VIH (70%)

VIL (20%)

Product specification

SAA7710T

SCK

WS

SD

MSB

LEFT

MSB

RIGHT

MBH173

Fig.5 I2S-bus timing and format.

For communication with external digital sources and or

additional external processors the I2S-bus digital interface

bus is used. It is a serial 3-line bus, with one line for data,

one line for clock and one line for the word select.

Figure 5 shows an excerpt of the Philips I2S-bus

specification interface report regarding the general timing

and format of I2S-bus. Word Select (WS) logic 0 means left

channel word, logic 1 means right channel word.

The serial data is transmitted in two’s complement with the

MSB first. One clock period after the negative edge of the

word select line the MSB of the left channel is transmitted.

Data is synchronised with the negative edge of the clock

and latched at the positive edge.

I2S-BUS INPUT CIRCUIT

The I2S-bus input circuits can be configured in the

following way using the SEL-IN1/IN2 bit (see Table 4):

1. I2S input 1 is master

(SEL-IN1/IN2 bit = logic 0(default))

2. I2S input 2 is master (SEL-IN1/IN2 bit = logic 1).

The incoming bit-clock frequency defines the accuracy in

terms of number of bits of the incoming data samples.

The input circuit is designed to accept any number of bits

per channel up to a maximum of 18 bits. The accepted

data format is MSB-first.

1998 Mar 13

8

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