SAA7710T データシートの表示（PDF） - Philips Electronics

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SAA7710T

Dolby* Pro Logic Surround; Incredible Sound

Philips Electronics 

Philips Semiconductors

Dolby* Pro Logic Surround;

Incredible Sound

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SAA7710T

Table 1 Data Accuracy in I2S-bus Interface

INCOMING DATA WIDTH

I2S-BUS IN DATA WIDTH

A < 18

A

B ≥18

18

I2S-BUS OUT DATA WIDTH

A

18

THE I2S-BUS OUTPUT INTERFACE

The I2S-bus data output interfaces (see Fig.1) I2S OUT 1,

I2S OUT 2 and I2S OUT 3 use the same I2S-bus data

signals which are selected by the input switch circuit. The

I2S-bus WS and BCK output signals remain in phase with

the external input signals at all times. The output data is

1/fs cycle delayed relative to the input data. The selected

word-select and bit-clock are included as part of the output

interface: I2S_WSOUT, I2S_BCKOUT. These two output

signals can be 3-stated by setting the DIS_BCKWS bit

(see Table 4). The 3-state output of the I2S_DATAOUT3

signal can be enabled by setting the ENA_I2S3 bit (see

Table 4).

The timing diagram of the I2S-bus outputs is shown in

Fig.6. The timing details can be found in Chapter “AC

characteristics”.

handbook, full pagewidth

CL

WS

DATA (in)

DATA (out)

tLC

tHC

td1

tf

tr

tf

td2

ts2

DATA VALID

tr

MSB

I2S_BCKIN1, 2

I2S_BCKOUT

I2S_WSIN1, 2

I2S_WSOUT

I2S_DATAIN1, 2

td3

tr

tf

MSB

tacc

I2S_DATAOUT1, 2, 3

MGE755

Fig.6 Timing diagram of I2S-bus output interface.

1998 Mar 13

9

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