T4312816A データシートの表示（PDF） - Taiwan Memory Technology

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T4312816A

8M x 16 SDRAM 2M x 16bit x 4Banks Synchronous DRAM

Taiwan Memory Technology 

tm TE

CH

Preliminary T4312816A

DC CHARACTERISTICS

TA = 0 to 70°C , VIH(min)/VIL(max)=2.0V/0.8V

Speed version

Parameter Symbol

Unit

Test Condition

Note

-6 -7 -7.5 -8 -10

Operating Current

( One Bank Active)

ICC1

140

120

115

110

100

mA

Burst Length = 1

tRC≥tRC(min) ,tCC≥tCC(min),IOL= 0 mA

1,3

Precharge Standby ICC2P

Current in power-

down mode

ICC2PS

2

CKE ≤ VIL(max),tCC=15ns

mA

3

2

CKE ≤ VIL(max),CLK ≤ VIL(max), tCC =∞

Precharge Standby

Current in non

ICC2N

power-down mode

ICC2NS

20

8

CKE ≥ VIH(min), CS ≥ VIH(min),tCC=15ns

mA Input signals are changed one time during 30ns 3

CKE≥VIH(min),CLK ≤ VIL(min),tCC=∞

Input signals are stable

Active Standby ICC3P

Current in power-

down mode

ICC3PS

5

CKE ≤ VIL(max),tCC=15ns

mA

3

4

CKE ≤ VIL(max),CLK ≤ VIL(max),tCC=∞

Active Standby

Current in non

ICC3N

power-down mode

(One Bank Active) ICC3NS

30

20

CKE≥VIH(min), CS ≥VIH(min),tCC=15ns

mA Input signals are changed one time during 30ns 3

CKE≥VIH(min),CLK ≤ VIL(min),tCC=∞

Input signals are stable

Operating Current

(Burst Mode)

ICC4

150 130 125 120 110

CAS Latency 3 IOL=0 mA,Page Burst

mA

All Band Activated

1,3

150 130 125 120 110

CAS Latency 2

tCCD= tCCD(min)

Refresh Current ICC5

150 130 125 120 110 mA tRC ≥tRC(min)

2,3

Self refresh

Current

ICC6

2

mA CKE ≤ 0.2V

Note:

1. Measured with output open. Addresses are changed only one time during tCC(min) .

2. Refresh period is 64ms. Addresses are changed only one time during tCC(min) .

3. tCC : Clock cycle time.

tRC : Row cycle time.

tCCD : Column address to column address delay time.

TM Technology Inc. reserves the right

P. 5

to change products or specifications without notice.

Publication Date: APR. 2003

Revision: 0.B

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