TB62706 データシートの表示（PDF） - Toshiba

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TB62706

Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC

Toshiba 

PIN CONNECTION (Top view)

BLOCK DIAGRAM

TIMING DIAGRAM

TB62706BN/BF

Note:

Latches are level sensitive, not rising edges sensitive and not syncronus CLOCK.

Input of LATCH−terminal to H Level, data passes latches, and input to L level, data hold latches.

Input of ENABLE−terminal to H level, all output (OUT0~15) do off.

2

2006-06-14

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