TC826CBU データシートの表示（PDF） - Microchip Technology
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TC826CBU Datasheet PDF : 18 Pages
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TC826
4.0 THEORY OF OPERATION
4.1 Analog Section
In addition to the basic signal integrate and de-
integrate cycles discussed above, the TC826 incorpo-
rates an auto-zero cycle.This cycle removes buffer
amplifier, integrator, and comparator offset voltage
error terms from the conversion. A true digital zero
reading results without external adjusting potentiome-
ters. A complete conversion consists of three cycles:
an auto-zero, signal integrate and reference cycle
(Figure 4-1 and Figure 4-2).
4.1.1 AUTO-ZERO CYCLE
During the auto-zero cycle, the differential input signal
is disconnected from the circuit by opening internal
analog gates. The internal nodes are shorted to analog
common (internal analog ground) to establish a zero
input condition. Additional analog gates close a feed-
back loop around the offset voltage error compensation.
The voltage level established on CAZ compensates for
device offset voltages.
The auto-zero cycle length is 19 counts minimum.
Unused time in the de-integrate cycle is added to the
auto-zero cycle.
4.1.2 SIGNAL INTEGRATION CYCLE
The auto-zero loop is opened and the internal differen-
tial inputs connect to +IN and -IN. The differential input
signal is integrated for a fixed time period. The TC826
signal integration period is 20 clock periods or counts.
The externally set clock frequency is divided by 32
before clocking the internal counters. The integration
time period is:
EQUATION 4-1:
Where:
TSI =
32
FOSC
x 20
FOSC = External Clock Frequency
FIGURE 4-1:
TC826 ANALOG SECTION
REF IN
5
AZ
+Input 3
INT
CREF
6
TC826
DE-
DE+
RINT
CAZ
CINT
7
9
10
11
–
+
Buffer
Integrator
–
+
+
–
Comparator
AZ
VDD
8
CMPTR
To Digital Section
AZ
Analog 2
Common
-INPUT 4
DE+
DE-
AZ INT
INT
VDD
1µA
VDD
≈ 6.3V
From
AZ
Digital
INT
Control
DE+
Center
DE-
Analog Switch
≈ VDD – 2.9V
12
≈ VDD
DS21477B-page 8
© 2002 Microchip Technology Inc.
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