TRU050-GFCNA データシートの表示（PDF） - Vectron International

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TRU050-GFCNA

Complete VCXO based Phase-Locked Loop

Vectron International 

TRU050, VCXO Based PLL

VDD

Vd

−π

0

VDD/2

+π Relative

Phase (θe)

0V

Gain Slope = VDD/ 2π

Figure 5. Open Loop Phase Detector Transfer Curve

Recovered Clock and Data Alignment Outputs

The TRU050 is designed to recover an imbedded clock from an NRZ data signal and retime it with a data

pattern. In this application, the VCXO frequency is exactly the same frequency as the NRZ data rate and the

outputs are taken off Pin 11, RCLK, and Pin 12, RDATA. Under locked conditions, the falling edge of RCLK is

centered in the RDATA pattern. Also, there is a 1.5 clock cyle delay between DATAIN and RDATA. Figure 6

shows the relationship between the DATAIN, CLKIN, RDATA and RCLK.

Data In

Clock In

Data1

Recovered

Data

Recovered Clock

Data1

Figure 6. Clock and Data Timing Relationships for the NRZ data

Other RZ encoding schemes such as Manchester or AMI can be accomidated by using a TRU050 at twice

the baud rate.

Loss of Signal, LOS and LOSIN

The LOS circuit provides an output alarm flag when the DATAIN input signal is lost. The LOS output is

normally a logic low and is set to a logic high after 256 consecutive clock periods on CLKIN with no detected

DATAIN transitions. This signal can be used to either flag external alarm circuits and/or drive the TRU050’s

LOSIN input. When LOSIN is set to a logic high, the VCXO control voltage (pin 1) is switched to an internal

voltage which centers OUT1 and OUT2 to center frequency +/-75ppm. Also, LOS automatically closes the op

amp feedback which means the op-amp is a unity gain buffer and will produce a DC voltage equal to the +op

amp voltage (pin 4), usually VDD/2.

Vectron International, 267 Lowell Rd, Hudson NH 03051-4916

Page 5 of 15

Tel: 1-88-VECTRON-1 • Web: www.vectron.com

Rev: 12Aug2009

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