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UPB1507GV(1998) データシートの表示(PDF) - California Eastern Laboratories.

部品番号
コンポーネント説明
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UPB1507GV
(Rev.:1998)
CEL
California Eastern Laboratories. CEL
UPB1507GV Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN EXPLANATION
μPB1507GV
Pin name
IN
Applied
voltage
V
IN
GND
0
SW1
H/L
Pin
voltage
V
2.9
2.9
Functions and explanation
Signal input pin. This pin should be coupled to signal
source with capacitor (e.g. 1 000 pF) for DC cut.
Signal input bypass pin. This pin must be equipped
with bypass capacitor (e.g. 1 000 pF) to minimize
ground impedance.
Ground pin. Ground pattern on the board should be
formed as wide as possible to minimize ground
impedance.
Divide ratio input pin. The ratio can be determined by
following applied level to these pins.
SW2
SW1
SW2
H
L
H ÷64 ÷128
L ÷128 ÷256
VCC
OUT
NC
These pins should be equipped with bypass capacitor
(e.g. 1 000 pF) to minimize ground impedance.
4.5 to 5.5
Power supply pin. This pin must be equipped with
bypass capacitor (e.g. 10 000 pF) to minimize ground
impedance.
2.6 to 4.7 Divided frequency output pin. This pin is designed as
emitter follower output. This pin can be connected to
CMOS input due to 1.2 VP-P MIN output.
Non connection pin. This pin must be openned.
Pin no.
μPB1507GV
1
8
5
3
6
2
4
7
4

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