V62C3802048L データシートの表示（PDF） - Mosel Vitelic Corporation

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V62C3802048L

Ultra Low Power 256K x 8 CMOS SRAM

Mosel Vitelic Corporation  

V62C3802048L(L)

Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)

Address

DOUT

tRC

tAA

tOH

Data Valid

Timing Waveform of Read Cycle 2 (5,6,8,9) (CE1 Controlled)

tRC

CE1

OE

tOE

DOUT

tOLZ

tACE

tOHZ

tCHZ

Data Valid

tCLZ

tPD

Supply Current

tPU

ICC

50%

50%

ISB

Timing Waveform of Read Cycle 3 (3,6,8,9) (CE2 Controlled)

tRC

CE2

OE

tOE

DOUT

tOLZ

tACE

tOHZ

tCHZ

Data Valid

tCLZ

tPD

Supply Current

tPU

ICC

50%

50%

ISB

8

REV. 1.2 May 2001 V62C3802048L(L)

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