TS68HC901 データシートの表示（PDF） - STMicroelectronics

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TS68HC901

HCMOS MULTI-FUNCTION PERIPHERAL

STMicroelectronics 

TS68HC901

BUS OPERATION

The following paragraphs explain the control signals

and bus operation during data transfer operations

and reset.

DATA TRANSFER OPERATIONS.

Transfer of data between devices involves the follo-

wing pins: Register Select Bus - RS5 through RS1

Data Bus - D0 through D7 Control Signals The ad-

dress and data buses are separate parallel buses u-

sed to transfer data using an asynchronous bus

structure. In all cycles, the bus master assumes re-

sponsibility for deskewing all signals it issues at both

the start and end of a cycle. Additionally, the bus

master is responsible for deskewing the acknow-

ledge and data signals from the peripheral devices.

Read Cycle. To read a CMFP register, CS and DS

must be asserted, and R/W must be high. The

CMFP will place the content of the register which is

selected by the register select bus (RS1 through

RS5) on the data bus (D1 through D7) and then as-

sert DTACK. The register addresses are shown on

Figure 2. After the processor has latched the data, DS

is negated. The negation of either CS or DS will ter-

minate the read operation. The CMFP will drive

DTACK High and place it in the high-impedance state.

The timing for a read cycle is shown in figure 21.

Write Cycle. To write a register CS and DS must be

asserted, and R/W must be low. The CMFP will de-

code the address bus to determine which register is

selected. Then the register will be loaded with the

contents of the data bus and DTACK will be asser-

ted. When the processor recognizes DTACK, DS

will be negated. The write cycle is terminated when

either CS or DS is negated. The CMFP will drive

DTACK high and place it in the high-impedance state.

The timing for a write cycle is shown in figure 22.

INTERRUPT ACKNOWLEDGE OPERATION.

The CMFP has 16 interrupt sources, eight internal

and eight external. When an interrupt request is

pending, the CMFP will assert IRQ. In a vectored in-

terrupt scheme, the processor will acknowledge the

interrupt request by performing an interrupt acknow-

ledge cycle. IACK and DS will be asserted. The

CMFP responds to the IACK signal by placing a vec-

tor number on the lower eight bits of the data bus.

This vector number corresponds to the IRQ handler

for the particular interrupt requesting service. The

format of this vector number is given in figure 6.

When the CMFP asserts DTACK to indicate that va-

lid data is on the bus, the processor will latch the da-

ta and terminate the bus cycle by negating DS.

When either DS or IACK are negated, the CMFP will

terminate the interrupt acknowledge operation by

driving DTACK high and placing it in the high-impe-

dance state. Also, the data bus will be placed in the

high-impedance state. IRQ will be negated as a re-

sult of the IACK cycle unless additional interrupts

are pending.

The CMFP can be part of a daisy-chain interrupt

structure which allows multiple CMFPs to be placed

at the same interrupt level by sharing a common

IACK signal. A daisy-chain priority scheme is imple-

mented with IEI and IEO signals. IEI indicates that

no higher priority device is requesting interrupt ser-

vice. IEO signals lower priority devices that neither

this device nor any higher priority devices is reques-

ting service. To daisy-chain CMFPs, the highest

priority CMFP has its IEI tied low and successive

CMFPs have their IEI connected to the next higher

priority device’s IEO. Note that when the daisy-chain

7/42

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