XC2267-XXF66L データシートの表示（PDF） - Infineon Technologies

部品番号

コンポーネント説明

メーカー

XC2267-XXF66L

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance Volume 1 (of 2): Peripheral Units

Infineon Technologies 

XC2000 Derivatives

System Units (Vol. 1 of 2)

Preliminary

Architectural Overview

2.1

Basic CPU Concepts and Optimizations

The main core of the CPU consists of a set of optimized functional units including the

instruction fetch/processing pipelines, a 16-bit Arithmetic and Logic Unit (ALU), a 40-bit

Multiply and Accumulate Unit (MAC), an Address and Data Unit (ADU), an Instruction

Fetch Unit (IFU), a Register File (RF), and dedicated Special Function Registers (SFRs).

Single clock cycle execution of instructions results in superior CPU performance, while

maintaining C166 code compatibility. Impressive DSP performance, concurrent access

to different kinds of memories and peripherals boost the overall system performance.

CPU

Prefetch

Unit

Branch

Unit

FIFO

IDX0

IDX1

QX0

QX1

+/-

Multiply

Unit

+/-

MAH

MAC

PMU

CSP

IP

CPUCON1

CPUCON2

Return

Stack

IFU

VECSEG

TFR

Injection/

Exception

Handler

2-Stage

Prefetch

Pipeline

5-Stage

Pipeline

IPIP

QR0

QR1

+/-

MRW

MCW

MSW

MAL

DPP0

DPP1

DPP2

DPP3

SPSEG

SP

STKOV

STKUN

ADU

Division Unit

Multiply Unit

MDC

PSW

MDH

ZEROS

Bit-Mask-Gen.

Barrel-Shifter

+/-

MDL

ONES

ALU

CP

RR1155

RR114R415

R14

GGPPRRss

GPRs

RR11

RR00R1

R0

RF

Buffer

WB

DMU

Figure 2-2 CPU Block Diagram

User’s Manual

2-2

ArchitectureX2K, V1.0

PSRAM

Flash/ROM

DPRAM

R15

R14

GPRs

R1

R0

DSRAM

EBC

Peripherals

mca04917_x.vsd

V1.0, 2007-06

Share Link: