ZXLB1600 データシートの表示（PDF） - Zetex => Diodes

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ZXLB1600

LCD BIAS BOOST CONVERTER

Zetex => Diodes 

ZXLB1600

Device Description

The device is a flyback boost regulator, working in discontinuous mode.

Device Operation

With reference to the chip block diagram and typical application circuit:

Control loop operation

When ‘EN’ is high, the control circuits become active. The high side of the coil is connected to the

input via a large PMOS isolating switch (MP) and the low side to ground via a NMOS transistor (MN).

The current in the coil is allowed to build up to an internally defined level (nominally 300mA) before

MN is turned off. The energy stored in the coil is then transferred to the output capacitor (C1) via a

Schottky diode (SD). The output voltage is sensed at pin ‘SENSE’ by internal resistors R1 and R2

(which may be shunted externally at pin ‘FB’) and compared to a reference voltage (1.23V nominal). A

comparator senses when the output voltage is above that set by the reference and its output is used

to control the ‘off’ time of the output switch. The control loop is self-oscillating, producing fixed pulses

of 10us maximum width, at a frequency that varies in proportion to the output load current. This mode

of operation is known as Pulse Frequency Modulation (PFM)

Setting output voltage

The output voltage is equal to the voltage present on the ‘ADJ’ pin of the device multiplied by the

internal resistor network factor (R1+R2)/R1. The ADJ pin is connected to the internal reference

voltage of value VADJ(NOM), and by default will give a nominal output of 28V. However, if required, the

ADJ pin may be overdriven with an external dc voltage, in order to adjust the output voltage to a value

lower than the default value.

The reference voltage on the ADJ pin is switched into a low pass filter circuit when the EN pin is high

and the output of this filter drives the comparator within the control loop. By varying the duty cycle of

the EN signal, the control loop will see a voltage, which has an average value equal to the duty cycle

multiplied by the voltage present on the ADJ pin. This provides an alternative means of adjusting the

output voltage. It also allows the device to be both turned on and adjusted with a single signal at the

‘EN’ pin. The output voltage during this mode of operation will be VADJ x (R1+R2)/R1 x duty cycle.

To reduce standby current consumption, the internal reference is turned off when no signal is present

on the ‘EN’ pin

Further control over output voltage during either mode of operation is possible by shunting the internal

resistor network comprising R1 and R2 by means of external resistors connected to the SENSE and

FB pins.

Low Battery detection

A comparator driving an open drain NMOS output transistor performs the low battery flag function.

The detection threshold (battery voltage falling) is set internally to 2V nominal, but this can be

changed by shunting the internal potential divider with two external resistors at pin ’LBT’. Operation is

such that the output transistor will be turned on when the battery voltage falls below the detection

threshold. A small amount (nominal 20mV) of hysteresis is provided to aid clean switching. The low

battery detect circuit remains active when ‘EN’ is low.

DRAFT ISSUE J January 2002

ZXLB1600

5

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