DNC3X3625 データシートの表示（PDF） - Agere -> LSI Corporation

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DNC3X3625

Hex 10/100 Mbits/s Ethernet Transceiver Macrocell

Agere -> LSI Corporation 

Advance Data Sheet

March 2000

DNC3X3625

10/100 Mbits/s Ethernet Transceiver Macrocell

Signal Information (continued)

Table 6. Control/Status Signals (continued)

Signal

Type

Description

FASTTEST

I

Fast Test. This signal should be low for normal operation. When high, the

internal timers run faster than normal, with the speedup determined by

FASTSEL[1:0]

FASTSEL[1:0]

I

Fast Speed Select. When FASTTEST is high, the speedup of the timers

(10 Mbit/s NLP link, 10 Mbit/s jabber, reset timers, autonegotiation counters)

is as follows:

00 = No speedup.

01 = 16x speedup.

4

10 = 64x speedup.

11 = 256x speedup. (Autonegotiation does not work at this speedup.)

LITF_ENH

I

Enhanced Link Integrity Test Function. When this input is high, The link

will be deasserted when 31 Manchester violations have occurred.

SDFX[5:0]

PAD SDFX. Signal detect from fiber-optic receiver. This pad does not have to be

(optional I) bonded out if fiber mode is not used.

SECUR[5:0]

I

Security. When this input is high and MTX_EN is high, JAM pattern (55) is

transmitted.

ISOLATE[5:0]

I

Isolate. When this signal is high, the macrocell will come out of reset in

isolate mode per the IEEE standard. If this is low, then the macrocell will

come out of reset in normal mode. When isolated, all receive outputs are

low, and all transmit requests are ignored. While isolated, the macrcell will

respond to management transactions, detect, and transmit link pulses.

Register 0, bit 10, is used to put the transceiver in/out of isolate mode.

APFE_PIN[5:0]

I

Autopolarity Function Enable (Active Low). When this signal is set low

and the DNC3X3625 is operating at 10 Mbits/s, the autopolarity function will

determine if the TP link is wired with a polarity reversal:

s The DNC3X3625 will assert the autopolarity status (APS) bit (register 28,

bit 6) and correct the polarity reversal.

ELLE_PIN[5:0]

HBT_PIN[5:0]

LPBK_PIN[5:0]

NOLP_PIN[5:0]

LED_STR_EN

s If this signal is set high and the DNC3X3625 is operating at 10 Mbits/s,

the reversal will not be corrected.

I

Extended Line Length Enable. When this signal is set high, the receive

squelch level is reduced from a nominal 435 mV to 350 mV, allowing recep-

tion of signals with lower amplitude. This is the same function as register 30,

bit 4. The input and the register bit are ORed together.

I

Heartbeat Enable. When asserted high, this input will enable the heartbeat

function (serial mode). This is the same function as register 30, bit 5. The

input and the register bit are ORed together.

I

Loopback. When this signal is asserted high DNC3X3625 is in loopback

mode. No data transmission will take place on the media and any receive

data will be ignored. This is the same function as register 0, bit 14. The input

and the register bit are ORed together.

I

No Link Pulse Mode. Setting this signal high will allow 10 Mbits/s operation

with link pulses disabled. If the DNC3X3625 is configured for

100 Mbits/s operation, this signal is ignored. This is the same function as

register 30, bit 0. The input and the register bit are ORed together.

I

LED Stretch Enable. This pin, when low, disables stretching. When high,

the LED output is stretched to 42 ms minimum, unless LED_BLINK_EN is

high. This signal is ORed with register 29, bit 7.

11

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