WEDPN16M64VR-100BC データシートの表示（PDF） - White Electronic Designs => Micro Semi
部品番号
コンポーネント説明
メーカー
WEDPN16M64VR-100BC Datasheet PDF : 12 Pages
| |||
WEDPN16M64VR-XBX
HI-RELIABILITY PRODUCT
16Mx64 Registered Synchronous DRAM *ADVANCED
FEATURES
n Registered for enhanced performace of bus speeds
66 MHz - 133 MHz Commercial, Industrial Temperature Only
66 MHz - 125 MHz Military Temperature Only
n Package:
219 Plastic Ball Grid Array (PBGA), 32 x 25mm
n Single 3.3V ±0.3V power supply
n Fully Synchronous; all signals registered on positive edge of
system clock cycle
n Internal pipelined operation; column address can be changed
every clock cycle
n Internal banks for hiding row access/precharge
n Programmable Burst length 1,2,4,8 or full page
n 8192 refresh cycles
n Commercial, Industrial and Military Temperature Ranges
n Organized as 16M x 64
n Weight: WEDPN16M64VR-XBX - 2.5 grams typical
BENEFITS
n 37% SPACE SAVINGS
n 17% I/O Reduction
n Reduced part count
n Reduced trace lengths for lower parasitic capacitance
n Glue-less connection to memory controller/PCI Bridge
n Suitable for hi-reliability applications
n Laminate interposer for optimum TCE match
n Upgradeable to 32M x 64 density (contact factory for information)
*This data sheet describes a product under development, non-qualified, not fully
characterized, and is subject to change without notice.
GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS, dynamic
random-access, memory using 4 chips containing 268,435,456
bits. Each chip is internally configured as a quad-bank DRAM with
a synchronous interface. Each of the chips 67,108,864-bit banks
is organized as 8,192 rows by 512 columns by 16 bits. The MCP
also incorporates two 16-bit universal bus drivers for input control
signals and addresses.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
grammed number of locations in a programmed sequence.
Accesses begin with the registration of an ACTIVE command,
which is then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE command are
used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0-12 select the row). The address bits registered
coincident with the READ or WRITE command are used to select
the starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate
option. An AUTO PRECHARGE function may be enabled to provide
a self-timed row precharge that is initiated at the end of the burst
sequence.
The 1Gb SDRAM uses an internal pipelined architecture to achieve
high-speed operation. This architecture is compatible with the 2n rule
of prefetch architectures, but it also allows the column address to be
changed on every clock cycle to achieve a high-speed, fully random
access. Precharging one bank while accessing one of the other three
banks will hide the precharge cycles and provide seamless, high-
speed, random-access operation.
The 1Gb SDRAM is designed to operate in 3.3V, low-power memory
systems. An auto refresh mode is provided, along with a power-
saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer substan-
tial advances in DRAM operating performance, including the ability to
synchronously burst data at a high data rate with automatic column-
address generation, the ability to interleave between internal banks
in order to hide precharge time and the capability to randomly change
column addresses on each clock cycle during a burst access.
Sept. 2001 Rev. 1
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
Share Link: 