WEDPN16M64VR-100BC データシートの表示（PDF） - White Electronic Designs => Micro Semi
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WEDPN16M64VR-100BC Datasheet PDF : 12 Pages
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FIG. 3 MODE REGISTER DEFINITION
A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
Unused Reserved* WB Op Mode CAS Latency BT Burst Length
Mode Register (Mx)
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
0
1
M6 M5 M4
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M8
M7
M6-M0
Operating Mode
0
0
Defined
Standard Operation
-
-
-
All other states reserved
M9
Write Burst Mode
0
Programmed Burst Length
1
Single Location Access
WEDPN16M64VR-XBX
TABLE 1 - BURST DEFINITION
Burst Starting Column Order of Accesses Within a Burst
Length
Address
Type = Sequential Type = Interleaved
2
4
8
Full
Page
(y)
A0
0
0-1
1
1-0
A1 A0
00
0-1-2-3
01
1-2-3-0
10
2-3-0-1
11
3-0-1-2
A2 A1 A0
000
0-1-2-3-4-5-6-7
001
1-2-3-4-5-6-7-0
010
2-3-4-5-6-7-0-1
011
3-4-5-6-7-0-1-2
100
4-5-6-7-0-1-2-3
101
5-6-7-0-1-2-3-4
110
6-7-0-1-2-3-4-5
111
7-0-1-2-3-4-5-6
n = A0-9/8/7 Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
(location 0-y)
Cn - 1,
Cn
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
NOTES:
1. For full-page accesses: y = 512.
2. For a burst length of two, A1-8 select the block-of-two burst; A0 selects the
starting column within the block.
3. For a burst length of four, A2-8 select the block-of-four burst; A0-1 select the
starting column within the block.
4. For a burst length of eight, A3-8 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-8 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-8 select the unique column to be accessed, and
Mode Register bit M3 is ignored.
5
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