MACHLV210-24 データシートの表示（PDF） - Lattice Semiconductor
部品番号
コンポーネント説明
メーカー
MACHLV210-24 Datasheet PDF : 29 Pages
| |||
CAPACITANCE (Note 1)
Parameter
Symbol
Parameter Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
VCC = 3.3 V, TA = 25°C, f = 1 MHz
Typ Unit
6
pF
8
pF
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 2)
Parameter
Symbol
Parameter Description
-12
Min
Max
tPD
Input, I/O, or Feedback to Combinatorial Output
12
Setup Time from Input, I/O,
tS
or Feedback to Clock
D-type
9
T-type
10
tH
Register Data Hold Time
0
tCO
Clock to Output
8
tWL
Clock
tWH
Width
LOW
5
HIGH
6
External Feedback
Maximum
fMAX
Frequency
(Note 1) Internal Feedback (fCNT)
D-type
T-type
D-type
T-type
58.8
55.6
83.3
76.9
No Feedback (fCNT)
tSL
Setup Time from Input, I/O, or Feedback to Gate
90.9
9
tHL
Latch Data Hold Time
0
tGO
Gate to Output
9
tGWL
Gate Width LOW
5
tPDL
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
15
tSIR
Input Register Setup Time
2
tHIR
Input Register Hold Time
1.5
tICO
Input Register Clock to Combinatorial Output
15
tICS
Input Register Clock to Output Register Setup
D-type
12
T-type
13
tWICL
tWICH
Input Register
Clock Width
LOW
5
HIGH
6
fMAXIR
Maximum Input Register Frequency 1/(tWICL + tWICH)
90.9
tSIL
Input Latch Setup Time
2
tHIL
Input Latch Hold Time
1.5
tIGO
Input Latch Gate to Combinatorial Output
17
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
19
tSLL
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Output Latch Gate
10
tIGS
Input Latch Gate to Output Latch Setup
13
Unit
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
10
MACHLV210-12 (Com’l)
Share Link: 