HD74ALVC16835TEL データシートの表示（PDF） - Renesas Electronics
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HD74ALVC16835TEL Datasheet PDF : 12 Pages
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HD74ALVC16835
18-bit Universal Bus Driver with 3-state Outputs
REJ03D0053-0700
(Previous: ADE-205-192E)
Rev.7.00
Apr 07, 2006
Description
The HD74ALVC16835 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation.
Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch
enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is
low, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the outputs
are in the high impedance state.
To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pullup
register; the minimum value of the register is determined by the current sinking capability of the driver.
Features
• Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Ordering Information
Part Name
Package Type
HD74ALVC16835TEL TSSOP-56 pin
Package Code
(Previous code)
PTSP0056KA-A
(TTP-56DAV)
Package
Abbreviation
T
Taping Abbreviation
(Quantity)
EL (1,000 pcs / Reel)
Function Table
Inputs
OE
LE
CLK
A
Output Y
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
L
L
H
X
L
L
L
X
H
Y0 *1
Y0 *2
H : High level
L : Low level
X : Immaterial
Z : High impedance
↑ : Low to high transition
Notes: 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high
before LE went low.
2. Output level before the indicated steady-state input conditions were established.
Rev.7.00 Apr 07, 2006 page 1 of 11
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