MC12093DR2G データシートの表示（PDF） - ON Semiconductor
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MC12093DR2G Datasheet PDF : 5 Pages
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MC12093
C1
50W
C2
VCC
IN
SB
SW1
SW2
IN
OUT
GND
VCC = 2.7 to 5.5 V
C3
EXTERNAL
COMPONENTS
C1 = C2 = 1000 pF
C3 = 0.1 mF
C4
C4 = 2.0 pF Load
Figure 2. AC Test Circuit
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
N/A
N/A
> 4 kV
> 200 V
> 2 kV
Pb Pkg
Pb−Free Pkg
Level 1
Level 1
Level 1
Level 1
UL 94 V−0 @ 0.125 in
125 Devices
Table 3. MAXIMUM RATINGS
Symbol
Rating
Value
Unit
VCC
Power Supply Voltage, Pin 2
−0.5 to 6.0
Vdc
TA
Operating Temperature Range
−40 to 85
°C
Tstg
Storage Temperature Range
−65 to 150
°C
IO
Maximum Output Current, Pin 4
4.0
mA
qJC
Thermal Resistance (Junction−to−Case) (Note 2) DFN8
35 to 40
°C/W
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
NOTE: ESD data available upon request.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power). For DFN8 only, thermal exposed pad must be connected to a sufficient thermal
conduit. Electrically connect to the most negative supply (GND) or leave unconnected, floating open.
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