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WM8716EDS データシートの表示(PDF) - Wolfson Microelectronics plc

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WM8716EDS
Wolfson
Wolfson Microelectronics plc Wolfson
WM8716EDS Datasheet PDF : 21 Pages
First Prev 11 12 13 14 15 16 17 18 19 20
Production Data
ML/I2S (PIN 28)
WM8716
MC/DM1 (PIN 27)
MD/DM0 (PIN 26)
B15 B14 B13
B2 B1 B0
Figure 6 Three-Wire Serial Interface
REGISTER MAP
WM8716 controls the special functions using 4 program registers, which are 16-bits long. These
registers are all loaded through input pin MD/DM0. After the 16 data bits are clocked in, ML/I2S is
used to latch in the data to the appropriate register. Table 5 shows the complete mapping of the
4 registers. Note that in hardware differential mode and 8X modes, software control is not available.
The hardware differential mode (Diff[1:0]) clock loss detector disable (CDD) can only be accessed by
writing to M2[8:5] with the pattern 1111. Register M4 is then accessible by setting A[2:0] to 110.
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
M0 -
-
-
- A2 (0) A1(0) A0(0) LDL AL7 AL6 AL5 AL4 AL3 AL2 AL1 AL0
M1 -
-
-
- A2(0) A1(0) A0(1) LDR AR7 AR6 AR5 AR4 AR3 AR2 AR1 AR0
M2 -
-
-
- A2(0) A1(1) A0(0) -
-
-
- IW1 IW0 OPE DEM MUT
M3 -
-
-
- A2(0) A1(1) A0(1) IZD SF1 SF0 CK0 REV SR0 ATC LRP I2S
M4 -
-
-
- A2(1) A1(1) A0(0) -
- CDD DIFF1 DIFF0 -
-
-
-
Table 5 Mapping of Program Registers
REGISTER
0
1
2
3
4
BITS
[7:0]
8
[7:0]
8
0
1
2
[4:3]
0
1
2
3
4
5
[7:6]
8
[5:4]
6
NAME
AL[7:0]
LDL
AR[7:0]
LDR
MUT
DEM
OPE
IW[1:0]
I2S
LRP
ATC
SR0
REV
CKO
SF[1:0]
IZD
DIFF
CDD
Table 6 Register Bit Descriptions
DEFAULT
FF
0
FF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DESCRIPTION
Attenuation data for left channel.
Attenuation data load control for left channel.
Attenuation data for right channel.
Attenuation data load control for right channel.
Left and right DACs soft mute control.
De-emphasis control.
Left and right DACs operation control.
Input audio data bit select.
Audio data format select.
Polarity of LRCIN select.
Attenuator control.
Digital filter slow roll-off select.
Output phase reverse.
CLKO frequency select.
Sampling rate select.
Infinite zero detection circuit control.
Differential output mode.
Clock loss detector disable.
WOLFSON MICROELECTRONICS LTD
PD Rev 3.1 April 2001
11

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