M80C286 データシートの表示（PDF） - Intel

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M80C286

HIGH PERFORMANCE CHMOS MICROPROCESSOR WITH MEMORY MANAGEMENT AND PROTECTION

Intel 

M80C286

Figure 31 Example Power-Down Sequence

271103 – 29

THE POWER-DOWN FEATURE OF

THE M80C286

The M80C286 unlike the HMOS part can enter into

a power-down mode By stopping the processor

CLK the processor will enter a power-down mode

Once in the power-down mode all M80C286 outputs

remain static (the same state as before the mode

was entered) The M80C286 D C specification ICCS

rates the amount of current drawn by the processor

when in the power-down mode When the CLK is

reapplied to the processor it will resume execution

where it was interrupted

In order to obtain maximum benefits from the power-

down mode certain precautions should be taken

When in the power-down mode all M80C286 out-

puts remain static and any output that is turned on

and remains in a HIGH condition will source current

when loaded Best low-power performance can be

obtained by first putting the processor in the HOLD

condition (turning off all of the output buffers) and

then stopping the processor CLK in the phase 2

state In this condition any output that is loaded will

source only the ‘‘Bus Hold Sustaining Current’’

When coming out of power-down mode the system

CLK must be started with the same polarity in which

it was stopped An example power down sequence

is shown in Figure 31

BUS HOLD CIRCUITRY

To avoid high current conditions caused by floating

inputs to peripheral CMOS devices and eliminate the

need for pull-up down resistors ‘‘bus-hold’’ circuitry

has been used on all tri-state M80C286 outputs See

Table 16 for a list of these pins and Figures 32 and

33 for a complete description of which pins have bus

hold circuitry These circuits will maintain the last

valid logic state if no driving source is present (i e

an unconnected pin or a driving source which goes

to a high impedance state) To overdrive the ‘‘bus

hold’’ circuits an external driver must be capable of

supplying the maximum ‘‘Bus Hold Overdrive’’ sink

or source current at valid input voltage levels Since

this ‘‘bus hold’’ circuitry is active and not a

Pull-Up Pull-Down

When stopping the processor clock minimum clock

high and low times cannot be violated (no glitches

on the clock line)

Violating this condition can cause the M80C286 to

erase its internal register states Note that all inputs

to the M80C286 (CLK HOLD PEREQ RESET

READY INTR NMI BUSY and ERROR) should be

at VCC or VSS any other value will cause the

M80C286 to draw additional current

271103 – 30

Figure 32 Bus Hold Circuitry Pins 36 – 51 66 – 67

31

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