GAL16V8C-10LJI データシートの表示（PDF） - Lattice Semiconductor

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GAL16V8C-10LJI

High Performance E2CMOS PLD Generic Array Logic™

Lattice Semiconductor 

Specifications GAL16V8

COMPLEX MODE

In the Complex mode, macrocells are configured as output only

or I/O functions.

Architecture configurations available in this mode are similar to

the common 16L8 and 16P8 devices with programmable polarity

in each macrocell.

Up to six I/O's are possible in this mode. Dedicated inputs or

outputs can be implemented as subsets of the I/O function. The

two outer most macrocells (pins 12 & 19) do not have input ca-

pability. Designs requiring eight I/O's can be implemented in the

Registered mode.

All macrocells have seven product terms per output. One product

term is used for programmable output enable control. Pins 1 and

11 are always available as data inputs into the AND array.

The JEDEC fuse numbers including the UES fuses and PTD fuses

are shown on the logic diagram on the following page.

XOR

Combinatorial I/O Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 13 through Pin 18 are configured to this function.

XOR

Combinatorial Output Configuration for Complex Mode

- SYN=1.

- AC0=1.

- XOR=0 defines Active Low Output.

- XOR=1 defines Active High Output.

- AC1=1.

- Pin 12 and Pin 19 are configured to this function.

Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.

3-70

1996 Data Book

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