HV506DG データシートの表示（PDF） - Supertex Inc
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HV506DG Datasheet PDF : 9 Pages
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Functional Block Diagram
VDD
OE
POL
LVDD
DRIOA
CLK
S/R
DIR
HV506
Output
HVOUT1
Output
HVOUT2
DRIOB
LVSS
Function Table
I/O Relations
CLK
Inputs
DIR S/R Data
POL
OE
O/P HIGH
X
X
H
H
L
O/P OFF
X
X
L
X
L
O/P LOW
X
X
H
L
L
O/P OFF
X
X
X
X
H
Note:
H = logic high level, L = logic low level, X = irrelevant
Output
VSS
HVOUT40
DP
DN
HV Outputs
H
HIGH-Z
L
All O/P HIGH-Z
Output Sequence Operation Table
DIR Data Reset In Data Reset Out
L
DRIOB
H
DRIOA
DRIOA1
DRIOB2
Notes:
1. DRIOA is DRIOBdelayed by 40 clock pulses.
2. DRIOB is DRIOA delayed by 40 clock pulses.
3. Reference to chip layout drawing.
HVOUT # Sequence
40 → 1
1 → 40
Direction3
6
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