M34C00-WDW6T データシートの表示（PDF） - STMicroelectronics

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M34C00-WDW6T

3 x 128 bit Serial I²C Bus EEPROM For ee-Tags

STMicroelectronics 

M34C00

Figure 2A. SO and TSSOP Connections

NC

NC

NC

VSS

M34C00

1

8

2

7

3

6

4

5

AI03395B

VCC

NC

SCL

SDA

Note: 1. NC = Not Connected

When data is read by the bus master, the bus

master acknowledges the receipt of the data byte

in the same way. Data transfers are terminated by

a Stop condition after an Ack for Write, and after a

NoAck for Read.

Power On Reset: VCC Lock-Out Write Protect

In order to prevent data corruption and inadvertent

Write operations during Power-up, a Power On

Reset (POR) circuit is included. The internal reset

is held active until VCC has reached the POR

threshold value, and all operations are disabled –

the device will not respond to any command. In the

same way, when VCC drops from the operating

voltage, below the POR threshold value, all

operations are disabled and the device will not

respond to any command. A stable and valid VCC

must be applied before applying any logic signal.

These devices are compatible with the I2C

memory standard. This is a two wire serial

interface that uses a bi-directional data bus and

serial clock. The device carries a built-in 4-bit

Device Type Identifier code (1010) in accordance

with the I2C bus definition to access the memory

area and a second Device Type Identifier code

(0110) to access the Protection Register.

The device behaves as a slave in the I2C protocol,

with all memory operations synchronized by the

serial clock. Read and Write operations are

initiated by a Start condition, generated by the bus

master. The Start condition is followed by a Device

Select code and RW bit (as described in Table 3),

terminated by an acknowledge bit.

When writing data to the memory, the device

inserts an acknowledge bit during the 9th bit time,

following the bus master’s 8-bit transmission.

SIGNAL DESCRIPTION

Serial Clock (SCL)

This signal is used to strobe all data in and out of

the device. In applications where this line is used

by slave devices to synchronize the bus to a

slower clock, the bus master must have an open

drain output, and a pull-up resistor must be

connected from Serial Clock (SCL) to VCC. (Figure

3 indicates how the value of the pull-up resistor

can be calculated). In most applications, though,

this method of synchronization is not employed,

and so the pull-up resistor is not necessary,

provided that the bus master has a push-pull

(rather than open drain) output.

Serial Data (SDA)

This bi-directional signal is used to transfer data in

or out of the device. It is an open drain output that

may be wire-OR’ed with other open drain or open

Table 2. Absolute Maximum Ratings 1

Symbol

Parameter

Value

Unit

TA

Ambient Operating Temperature

–40 to 85

°C

TSTG

Storage Temperature

–65 to 150

°C

SOT23: t.b.d.

t.b.d.

TLEAD

Lead Temperature during Soldering SO: 20 seconds (max) 2

235

°C

TSSOP: 20 seconds (max) 2

235

VIO

Input or Output range

–0.6 to 6.5

V

VCC

Supply Voltage

–0.3 to 6.5

V

VESD

Electrostatic Discharge Voltage (Human Body model) 3

4000

V

Note: 1. Except for the rating “Operating Temperature Range”, stresses above those listed in the Table “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions

above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-

tions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents.

2. IPC/JEDEC J-STD-020A

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)

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