M34C00-WDW6T データシートの表示（PDF） - STMicroelectronics
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M34C00-WDW6T Datasheet PDF : 15 Pages
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M34C00
Table 5. DC Characteristics (TA = –40 to 85 °C; VCC = 2.5 to 5.5 V)
Symbol
Parameter
Test Condition
ILI
Input Leakage
Current
SCL, SDA
0 V ≤ VIN ≤ VCC
ILO Output Leakage Current
0 V ≤ VOUT ≤ VCC, SDA in Hi-Z
ICC Supply Current
VCC =5.5V, fc=400kHz (rise/fall time <
30ns)
VCC =2.5V, fc=400kHz (rise/fall time <
30ns)
ICC1
Supply Current
(Stand-by)
VIN = VSS or VCC , VCC = 5.5 V
VIN = VSS or VCC , VCC = 2.5 V
VIL
Input Low
Voltage
SCL, SDA
VIH
Input High
Voltage
SCL, SDA
VOL
Output Low
Voltage
IOL = 3 mA, VCC = 5.5 V
IOL = 2.1 mA, VCC = 2.5 V
Min.
Max. Unit
± 2 µA
± 2 µA
2
mA
–0.3
1
mA
2
µA
1
µA
0.3VCC V
0.7VCC VCC+1 V
0.4
V
0.4
V
Table 6. AC Characteristics
M34C00
Symbol
Alt.
Parameter
VCC=2.5 to 5.5V
TA = –40 to 85°C
Min
Max
Unit
tCH1CH2
tR
Clock Rise Time
300
ns
tCL1CL2
tF
Clock Fall Time
300
ns
tDH1DH2 2
tR
SDA Rise Time
20
300
ns
tDL1DL2 2
tF
SDA Fall Time
20
300
ns
tCHCL
tHIGH Clock Pulse Width High
600
ns
tCLCH
tLOW Clock Pulse Width Low
1.3
µs
tCHDX 1
tSU:STA START Set-up Time
600
ns
tDLCL
tHD:STA START Hold Time
600
ns
tDXCX
tSU:DAT SDA In Set-up Time
100
ns
tCLDX
tHD:DAT SDA In Hold Time
0
µs
tCHDH
tSU:STO STOP Set-up Time
600
ns
tDHDL
tBUF Time the bus must be free between STOP and next START
1.3
µs
tCLQV 3
tAA
Clock Low to SDA Out Valid
200
900
ns
tCLQX
tDH SDA Out Hold Time after Clock Low
200
ns
fC
fSCL Clock Frequency
400
kHz
tW
tWR
Write Time
10
ms
Note: 1. For a reStart condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
9/15
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