MU9C1485A-70TCC データシートの表示（PDF） - MUSIC Semiconductors
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MU9C1485A-70TCC Datasheet PDF : 28 Pages
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WidePort LANCAM® Family
FUNCTIONAL DESCRIPTION Continued
address of the Highest-Priority Matching location in that
device, concatenated with its page address, along with
flags indicating internal match, multiple match, and full.
When the Status register is read with a Command Read
cycle, the device with the Highest-priority match will
respond, outputting the System Match address to the DQ
bus. The internal Match (/MA) and Multiple match (/MM)
flags are also output on pins. Another set of flags (/MF
and /FF) that are qualified by the match and full flags of
previous devices in the system are also available directly
on output pins, and are independently daisy-chained to
provide System Match and Full flags in vertically cascaded
LANCAM arrays. In such arrays, if no match occurs during
a comparison, read access to the memory and all the
registers except the Next Free register is denied to prevent
device contention. In a daisy chain, all devices will respond
to Command and Data Write cycles, depending on the
conditions shown in Tables 6a and 6b, unless the operation
involves the Highest-Priority Match address or the Next
Free address; in which case, only the specific device
having the Highest-Priority match or the Next Free
address will respond.
A Page Address register in each device simplifies vertical
expansion in systems using more than one LANCAM. This
register is loaded with a specific device address during
system initialization, which then serves as the higher-order
address bits. A Device Select register allows the user to
target a specific device within a vertically cascaded system
by setting it equal to the Page Address Register value, or
to address all the devices in a string at the same time by
setting the Device Select value to FFFFH.
Figure 1a shows expansion using a daisy chain. Note that
system flags are generated without the need for external
logic. The Page Address register allows each device in the
vertically cascaded chain to supply its own address in the
event of a match, eliminating the need for an external priority
encoder to calculate the complete Match address at the
expense of the ripple-through time to resolve the highest-
priority match. The Full flag daisy-chaining allows
Associative writes using a Move to Next Free Address
instruction which does not need a supplied address.
Figure 1b shows an external PLD implementation of a simple
priority encoder that eliminates the daisy chain ripple-
through delays for systems requiring maximum performance
from many CAMS.
32
D Q 31-0
/E
/W
/C M
/EC
D Q 31-0
/E
/W
/C M
W ide por t
L AN C AM
/EC
/MI
/ FI
/ FF
/MF
Vcc
V cc
/ MI
Wide P ort
LANCAM
/ MA
PLD
D Q 31-0
/E
/W
/C M
W ide por t
L AN C AM
/EC
/MI
/ FI
/ FF
/MF
/ MI
Wide P ort
LANCAM
/ MA
D Q 31-0
/E
/W
/C M
W ide por t
L AN C AM
/EC
/MI
/ FI
/ FF
/MF
S YS TE M F U L L
S YS TE M MATC H
Figure 1a: Vertical Cascading
Rev. 2
6
/ MI
Wide P ort
LANCAM
/ MA
/ MI
Wide P ort
LANCAM
/ MA
S Y S TE M
M A TC H
Figure 1b: External Prioritizing
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