HEF4541BP データシートの表示（PDF） - NXP Semiconductors.
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HEF4541BP Datasheet PDF : 17 Pages
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NXP Semiconductors
HEF4541B
Programmable timer
Table 10. Dynamic power dissipation
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C.
Symbol
Parameter
VDD Typical formula
Per package
PD
dynamic power dissipation
5 V PD = 1300 × fi + (fo × CL × VDD2) μW
10 V PD = 5300 × fi + (fo × CL × VDD2) μW
15 V PD = 12000 × fi + (fo × CL × VDD2) μW
Using the on-chip oscillator
PD(Tot)
Total dynamic power dissipation
5V
10 V
15 V
PD = 1300 × fosc + foCLVDD2 + 2CTCVDD2 fosc + 10VDD μW
PD = 5300 × fosc + foCLVDD2 + 2CTCVDD2 fosc + 100VDD μW
PD = 12000 × fosc + foCLVDD2 + 2CTCVDD2 fosc + 400VDD μW
[1] fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V;
fosc = oscillator frequency in MHz; CTC = timing capacitance in pF.
11. Waveforms
VI
RS input
VSS
VOH
O output
VOL
VI
MR input
VSS
(1)
1/fclk(max)
VM
tPLH
tWH(min)
tWL(min)
VM
tWH(min)
tPHL
aaa-003391
VOL and VOH are typical output voltage levels that occur with the output load.
Measurement are points given in Table 11, the test circuit in Figure 5 and the test data in Table 12
(1) 2n pulses as selected by address inputs (A0, A1).
Fig 4. Propagation delay clock (RS) to output (O), clock pulse width and maximum clock frequency
Table 11. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
HEF4541B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 June 2012
© NXP B.V. 2012. All rights reserved.
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