LSH32 データシートの表示（PDF） - LOGIC Devices Incorporated

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LSH32

32-bit Cascadable Barrel Shifter

LOGIC Devices Incorporated 

DEVICES INCORPORATED

LSH32

32-bit Cascadable Barrel Shifter

tially the LSH32s are arranged in

multiple rows or banks such that the

inputs to successive rows are left-

shifted by 16 positions. The outputs

of each row are multiplexed onto a

three-state bus. The normalization

problem then reduces to selecting

from among the several banks that

one which has the first non-zero bit

of the input value among its 16 most

significant positions. If the most

significant one in the input file was

within the upper 16 locations of a

given bank, the SO4 output of the

most significant slice in that bank will

be low. Single clock normalization

can thus be accomplished simply by

enabling onto the three-state output

bus the highest priority bank in which

this condition is met. In this way the

input word will be normalized

regardless of the number of shift

positions required to accomplish this.

The number of shift positions can be

determined simply by concatenation

of the SO3–SO0 outputs of the most

significant slice in the selected row

with the encoded Output Enable-bits

determining the row number. Note

that lower rows need not be fully

populated. This is because they

represent left shifts in multiples of 16

positions, and the lower bits of the

output word will be zero filled. In

order to accomplish this zero fill, the

least significant device in each row is

always enabled, and the row select is

instead connected to the SI4 input.

This will force the shift length of the

least significant device to a value

greater than 15 whenever the row

containing that device is not selected.

This results in zero fill being accom-

plished by the equivalently positioned

slice in a higher bank, as shown in the

diagram.

BLOCK FLOATING POINT

With a small amount of external logic,

block floating point operations are

easily accomplished by the LSH32.

Data resulting from a vector operation

are applied to the LSH32 with the

NORM-input deasserted. The SO4–

SO0 outputs fill then represent the

normalization shift distance for each

vector element in turn. By use of an

external latch and comparator, the

maximum shift distance encountered

across all elements in the vector is

saved for use in the next block opera-

tion (or block normalization). During

this subsequent pass through the data,

the shift code saved from the previous

pass is applied uniformly across all

elements of the vector. Since the

LSH32 is not used in the internal

normalize mode, this operation can be

pipelined, thereby obtaining the

desired shift distance for the next pass

while simultaneously applying the

normalization required from the

previous pass.

Special Arithmetic Functions

5

08/16/2000–LDS.32-Q

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