PEEL22LV10AZ-25 データシートの表示（PDF） - Anachip Corporation

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PEEL22LV10AZ-25

CMOS Programmable Electrically Erasable Logic Device

Anachip Corporation 

always be logically false and the I/O will function as a dedicated

input.

Input/Feedback Select

The PEEL™22LV10AZ macrocell also provides control over the

feedback path. The input/feedback signal associated with each I/ O

macrocell can be obtained from three different locations; from the

I/O input pin, from the Q output of the flip-flop (registered

feedback), or directly from the OR gate (combinatorial feed-

back).

Bi-directional I/O

The input/feedback signal is taken from the I/O pin when using the

pin as a dedicated input or as a bi-directional I/O. (Note that it is

possible to create a registered output function with a bi-direc-

tional I/O, refer to Figure 27).

Combinatorial Feedback

The signal-select multiplexer gives the macrocell the ability to

feedback the output of the OR gate, bypassing the output buffer,

regardless of whether the output function is registered or combi-

natorial. This feature allows the creation of asynchronous latches,

even when the output must be disabled. (Refer to configurations

5, 6, 7, and 8 in Figure 1.)

Registered Feedback

Feedback also can be taken from the register, regardless of

whether the output function is programmed to be combinatorial or

registered. When implementing a combinatorial output func- tion,

registered feedback allows for the internal latching of states

without giving up the use of the external output.

Operates in both 3 Volt and 3.3 Volt Systems

The PEEL™22LV10AZ is designed to operate with a VCC range of

2.7 to 3.6 Volts D.C. This allows operation in both 3 Volt

±10% (battery operated) and 3.3 Volt ±10% (power supply oper-

ated) systems. The propagation delay tPD is 5 ns slower at the

lower voltage, but this is typically not an issue in battery-oper-

ated systems (see “A.C. Electrical Characteristics” on page 64).

Zero Power Feature

The CMOS PEEL™22LV10AZ features “Zero-Power” standby

operation for ultra-low power consumption. With the “Zero-

Power” feature, transition-detection circuitry monitors the inputs,

I/Os (including CLK) and feedbacks. If these signals do not

change for a period of time greater than approximately two tPD’s,

the outputs are latched in their current state and the device auto-

matically powers down. When the next signal transition is

detected, the device will “wake up” for active operation until the

signals stop switching long enough to trigger the next power-

down. (Note that the tPD is approximately 5 ns. slower on the first

transition from sleep mode.)

As a result of the “Zero-Power” feature, significant power sav-

ings can be realized for combinatorial or sequential operations

when the inputs or clock change at a modest rate. See Figure 28.

When the PEEL™22LV10AZ is powered up, a built-in feature

holds the outputs in tri-state until Vcc reaches 2.2V. This pre-

vents output transitions during power-up.

Figure 28 Typical ICC vs. Input Clock Frequency

for the 22LV10AZ

Figure 27 Block Diagram of the

PEEL™22LV10AZ I/O Macrocell

Programmable Clock Options

A unique feature of the PEEL™22LV10AZ is a programmable

clock multiplexer that allows the user to select true or comple-

ment forms of either input pin or product-term clock sources.

100

AC = Asynchronous Clear

SP = Synchronous Preset

Anachip Corp.

www.anachip.com.tw

10

ICC

1in mA

0.1

0.01

0.01

4/10

0.1

1

10

100

Frequency in MHz

Rev. 1.0 Dec 16, 2004

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