M68Z128W データシートの表示（PDF） - STMicroelectronics

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M68Z128W

3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable

STMicroelectronics 

M68Z128W

Table 9. Low VCC Data Retention Characteristics

(TA = 0 to 70°C)

Symbol

Parameter

Test Condition

Min

ICCDR (1) Supply Current (Data Retention)

VCC = 3V, E1 ≥ VCC – 0.2V,

E2 ≤ 0.2V, f = 0

VDR (1) Supply Voltage (Data Retention) E1 ≥ VCC – 0.2V, E2 ≤ 0.2V, f = 0

1.4

tCDR (1,2) Chip Disable to Power Down

E1 ≥ VCC – 0.2V, E2 ≤ 0.2V, f = 0

0

tR (2) Operation Recovery Time

tAVAV

Note: 1. All other Inputs at VIH ≥ VCC – 0.2V or VIL ≤ 0.2V.

2. See Figure 10 for measurement points. Guaranteed but not tested. tAVAV is Read cycle time.

Typ

0.01

Max

2

Unit

µA

V

ns

ns

Figure 10. Low VCC Data Retention AC Waveforms

3.6V

VCC

3V

VDR > 1.4V

E1 2.2V

E2 0.8V

DATA RETENTION MODE

tCDR

E1 ≥ VDR – 0.2V

E2 ≤ 0.2V

tR

AI00664

9/12

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