M68Z512 データシートの表示（PDF） - STMicroelectronics

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M68Z512

4 Mbit (512 Kbit x 8) Low Power SRAM with Output Enable

STMicroelectronics 

M68Z512

WRITE Mode

The M68Z512 is in the WRITE mode whenever the

W and E pins are Low. Either the Chip Enable in-

put (E) or the WRITE Enable input (W) must be de-

asserted during Address transitions for subse-

quent WRITE cycles. Write begins with the con-

currence of Chip Enable being active with W low.

Therefore, address setup time is referenced to

WRITE Enable and Chip Enable as tAVWL and

tAVEH respectively, and is determined by the latter

occurring edge.

The WRITE Cycle can be terminated by the earlier

rising edge of E, or W.

If the Output is enabled (E = Low and G = Low),

then W will return the outputs to high impedance

within tWLQZ of its falling edge. Care must be taken

to avoid bus contention in this type of operation.

Data input must be valid for tDVWH before the ris-

ing edge of WRITE Enable, or for tDVEH before the

rising edge of E, whichever occurs first, and re-

main valid for tWHDX or tEHDX.

Figure 9. WRITE Enable Controlled, WRITE Mode AC Waveforms

A0-A18

E

W

DQ0-DQ7

Note: Output Enable (G) = Low.

tAVEL

tAVAV

VALID

tAVWH

tWHAX

tAVWL

tWLWH

tWLQZ

tWHDX

DATA INPUT

tDVWH

tWHQX

AI03037

9/15

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