MACH435-20 データシートの表示（PDF） - Lattice Semiconductor
部品番号
コンポーネント説明
メーカー
MACH435-20 Datasheet PDF : 30 Pages
| |||
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges (Note 1)
(continued)
Parameter
Symbol
Parameter Description
-12
Min
Max
tICS
Input Register Clock to Output Register Setup
D-type
9
T-type
10
tWICL
tWICH
Input Register Clock Width
LOW
6
HIGH
6
fMAXIR
Maximum Input Register Frequency
83.3
tSIL
Input Latch Setup Time
2
tHIL
Input Latch Hold Time
3
tIGO
Input Latch Gate to Combinatorial Output
16
tIGOL
Input Latch Gate to Output Through Transparent
Output Latch
18
Setup Time from Input, I/O, or Feedback Through
tSLLA
Transparent Input Latch to Product Term Output
4
Latch Gate
tIGSA
Input Latch Gate to Output Latch Setup Using
4
Product Term Output Latch Gate
tSLLS
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Global Output Latch Gate
9
tIGSS
Input Latch Gate to Output Latch Setup Using Global
9
Output Latch Gate
tWIGL
Input Latch Gate Width LOW
6
tPDLL
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
16
tAR
Asynchronous Reset to Registered or Latched Output
16
tARW
Asynchronous Reset Width (Note 1)
12
tARR
Asynchronous Reset Recovery Time (Note 1)
10
tAP
Asynchronous Preset to Registered or Latched Output
16
tAPW
Asynchronous Preset Width (Note 1)
12
tAPR
Asynchronous Preset Recovery Time (Note 1)
8
tEA
Input, I/O, or Feedback to Output Enable
2
12
tER
Input, I/O, or Feedback to Output Disable
2
12
Unit
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. See Switching Test Circuit at the end of this Data Book for test conditions.
2. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
where frequency may be affected.
3. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation.
10
MACH435-12 (Com’l)
Share Link: 