MACH435-12 データシートの表示（PDF） - Lattice Semiconductor

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MACH435-12

High-Density EE CMOS Programmable Logic

Lattice Semiconductor 

FUNCTIONAL DESCRIPTION

The MACH435 consists of eight PAL blocks connected

by a central switch matrix. There are 64 I/O pins and 6

dedicated input pins feeding the central switch matrix.

These signals are distributed to the eight PAL blocks for

efficient design implementation. There are 4 global

clock pins that can also be used as dedicated inputs.

All inputs and I/O pins have built-in pull-up resistors.

While it is always good design practice to tie unused

pins high, the pull-up resistors provide design security

and stability in the event that unused pins are left

disconnected.

The PAL Blocks

Each PAL block in the MACH435 (Figure 1) contains a

clock generator, a 90-product-term logic array, a logic

allocator, 16 macrocells, an output switch matrix, 8 I/O

cells, and an input switch matrix. The central switch

matrix feeds each PAL block with 33 inputs. This makes

the PAL block look effectively like an independent

“PAL33V16” with 8 to 16 buried macrocells.

In addition to the logic product terms, individual output

enable product terms and two PAL block initialization

product term are provided. Each I/O pin can be

individually enabled. All flip-flops that are in the

synchronous mode within a PAL block are initialized

together by either of the PAL block initialization product

terms.

The Central Switch Matrix and Input

Switch Matrix

The MACH435 central switch matrix is fed by the input

switch matrices in each PAL block. Each PAL block

provides 16 internal feedback signals, 8 registered input

signals, and 8 I/O pin signals to the input switch matrix.

Of these 32 signals, 24 decoded signals are provided to

the central switch matrix by the input switch matrix. The

central switch matrix distributes these signals back to

the PAL blocks in a very efficient manner that provides

for high performance. The design software automati-

cally configures the input and central switch matrices

when fitting a design into the device.

The Clock Generator

Each PAL block has a clock generator that can generate

four clock signals for use throughout the PAL block.

These four signals are available to all macrocells and

I/O cells in the PAL block, whether in synchronous or

asynchronous mode. The clock generator chooses the

four signals from the eight possible signals given by the

true and complement versions of the four global clock

pin signals.

The Product-Term Array

The MACH435 product-term array consists of 80

product terms for logic use, eight product terms for

output enable use, and two product terms for global PAL

block initialization. Each macrocell has a nominal

allocation of 5 product terms for logic, although the logic

allocator allows for logic redistribution. Each I/O pin has

its own individual output enable term. The initialization

product terms provide asynchronous reset or preset to

synchronous-mode macrocells in the PAL block.

The Logic Allocator

The logic allocator in the MACH435 takes the 80 logic

product terms and allocates them to the 16 macrocells

as needed. Each macrocell can be driven by up to 20

product terms if in synchronous mode, or 18 product

terms if in asynchronous mode. When product terms are

routed away from a macrocell, it is possible to route all 5

product terms away, which precludes the use of the

macrocell for logic generation; or it is possible to route

only 4 product terms away, leaving one for simple

function generation. The design software automatically

configures the logic allocator when fitting the design into

the device.

The logic allocator also provides an exclusive-OR gate.

This gate allows generation of combinatorial exclusive-

OR logic, such as comparison or addition. It allows

registered exclusive-OR functions, such as CRC gen-

eration, to be implemented more efficiently. It also

makes in possible to emulate all flip-flop types with a

D-type flip-flop. Register type emulation is automatically

handled by the design software.

Table 1 illustrates which product term clusters are

available to each macrocell within a PAL block. Refer to

Figure 1 for cluster and macrocell numbers.

MACH435-12/15/20, Q-20/25

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