ISL88705(2006) データシートの表示（PDF） - Intersil

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ISL88705
(Rev.:2006)

µP Supervisor with Watchdog Timer, Power-Fail Comparator, Manual Reset and Adjustable Power-On Reset

Intersil 

ISL88705, ISL88706, ISL88707, ISL88708, 8SL88716, ISL88813

Electrical Specifications Over the recommended operating conditions unless otherwise specified. (Continued)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

MANUAL RESET

VMRL

MR Input Voltage Low

VMRH MR Input Voltage High

tMR

MR Minimum Pulse Width

RPU

Internal MR Pull-Up Resistor

WATCHDOG TIMER (Note 4)

0.8

VDD-0.6

550

20

tWDT

tWDPS

VIL

VIH

VWDOL

Watchdog Time-out Period

WDI Minimum Pulse Width

Watchdog Input Voltage Low

Watchdog Input Voltage High

WDO Output Voltage Low

VWDOH WDO Output Voltage High

IWDT

Watchdog Input Current

POWER-FAIL DETECTION

VDD ≥ 3.3V, Sinking 2.5mA

VDD < 3.3V, Sinking 1.5mA

VDD ≥ 3.3V, Sourcing 2.5mA

VDD < 3.3V, Sourcing 1.5mA

1.0

100

0.7 x VDD

VDD-0.6

VDD-0.6

1.6

0.05

0.05

VDD-0.4

VDD-0.4

2.0

0.3 x VDD

0.40

0.40

1

VTHPFI PFI Input Threshold Voltage

PFIVTHHYST Hysteresis Voltage

VPFOL PFO Output Voltage Low

VDD ≥ 3.3V, Sinking 2.5mA

VDD < 3.3V, Sinking 1.5mA

VPFOH PFO Output Voltage High

VDD ≥ 3.3V, Sourcing 2.5mA

VDD < 3.3V, Sourcing 1.5mA

NOTE:

4. Applies to ISL88705, ISL88706, ISL88716, and ISL88813.

1.20

VDD-0.6

VDD-0.6

1.25

20

0.05

0.05

VDD-0.4

VDD-0.4

1.30

0.40

0.40

UNITS

V

V

ns

kΩ

s

ns

V

V

V

V

V

V

µA

V

mV

V

V

V

V

Principles of Operation

The ISL88705 - ISL88813 devices provide those functions

needed for monitoring critical voltages such as power-supply

and battery functions in microprocessor systems. Features of

these supervisors include Power On Reset control, Supply

Voltage Supervision, Power-Fail Detection and Manual Reset

Assertion. The integration of all these features along with high

reset threshold accuracy and low power consumption make

these devices ideal for portable or battery-powered equipment.

Power-On Reset (POR)

Applying power to the device activates a POR circuit which

asserts reset (i.e. RST goes high while RST goes low). These

signals provide several benefits:

• It prevents the system microprocessor from starting to

operate with insufficient voltage.

• It prevents the processor from operating prior to stabilization

of the oscillator.

• It ensures that the monitored device is held out of operation

until internal registers are properly loaded.

• It allows time for an FPGA to download its configuration prior

to initialization of the circuit.

The reset signals remain active until VDD rises above the

minimum voltage sense level for time period tPOR. This

ensures that the supply voltage has stabilized to sufficient

operating levels.

6

FN8092.3

December 6, 2006

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