ISL88705(2006) データシートの表示（PDF） - Intersil

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ISL88705
(Rev.:2006)

µP Supervisor with Watchdog Timer, Power-Fail Comparator, Manual Reset and Adjustable Power-On Reset

Intersil 

ISL88705, ISL88706, ISL88707, ISL88708, 8SL88716, ISL88813

Low Voltage Monitoring

These devices monitor both the voltage level of VDD and an

auxiliary voltage on PFI.

When IC is initially biased reset is asserted until the VDD

voltage is greater than the specific IC fixed-voltage trip point

for the tPOR duration of 200ms. At any subsequent time that

VDD does not exceed its voltage threshold, reset is once

again asserted, i.e. RST is high and RST is low.

Power Failure Monitor

These devices also have a Power-Failure Monitor that helps

to monitor an additional critical voltage on the Power-Fail

Input (PFI) pin. For example, the PFI pin could be used to

provide an early power-fail warning, detect a low-battery

condition, presence detection or simply monitor a power

supply other than +5V. The 1.25V threshold detector can be

adjusted using an external resistor divider network to provide

custom voltage monitoring of voltages greater than 1.25V,

according to the following formula (See Figure 1):

PFI VTH = 1.25 (R1 + R2/R2)

PFO goes low whenever PFI is less than the 1.25V (or user-

set) threshold voltage.

R1

VIN

R2

PFI

ISL8870X

FIGURE 1. CUSTOM VTH WITH RESISTOR DIVIDER ON PFI

Adjusting tPOR

On the ISL88707 and ISL88708, users can adjust the Power

On Reset timeout delay (tPOR) to many times the nominal tPOR

of 200ms. To do this, connect a capacitor between CPOR and

ground (see Figure 3). For example, connecting a 50pF

capacitor to CPOR will increase tPOR from 200ms to ~1.4s.

Care should be taken in PCB layout and capacitor placement in

order to reduce stray capacitance as much as possible, which

contributes to tPOR error.

CPOR

ISL88707, ISL88708

14

12

NORMALIZED tPOR vs CPOR (pF)

OPEN = 200ms

10

8

6

4

2

0

0 10 20 30 40 50 60 70 80 90 100

CPOR (pF)

FIGURE 3. ADJUSTING tPOR WITH A CAPACITOR

VDD

VTH1

1V

>tMR

MR

tPOR

tRPD

tPOR

tPOR

RST

RST

FIGURE 2. POWER-SUPPLY MONITORING TIMING DIAGRAM (WDI TRI-STATED)

7

FN8092.3

December 6, 2006

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