ISL88705(2006) データシートの表示（PDF） - Intersil

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ISL88705
(Rev.:2006)

µP Supervisor with Watchdog Timer, Power-Fail Comparator, Manual Reset and Adjustable Power-On Reset

Intersil 

ISL88705, ISL88706, ISL88707, ISL88708, 8SL88716, ISL88813

Parametric Performance

11.0

10.5

10.0

VDD = 5V

9.50

9.00

8.50

8.00

7.50

VDD = 3.3V

7.00

6.50

6.00

-40 -30 -20 -10 0 10 20 30 40 50 60 70 90

TEMPERATURE (°C)

FIGURE 6. IDD vs TEMPERATURE

4.70

4.65

4.60

VTH = 4.64V

4.55

4.50

4.45

4.40

4.36

VTH = 4.38V

4.30

4.25

4.20

-40 -30 -20 -10 0 10 20 30 40 50 60 70 90

TEMPERATURE (°C)

FIGURE 7. VTH1 vs TEMPERATURE FOR 5V SUPPLY

3.2

3.1

VTH = 3.09V

3.0

2.9

2.8

VTH = 2.92V

2.7

2.6

2.5

VTH = 2.63V

2.4

-40 -30 -20 -10 0 10 20 30 40 50 60 70 90

TEMPERATURE (°C)

FIGURE 8. VTH1 vs TEMPERATURE < 5V SUPPLY

9

1.2530

1.2525

1.2520

1.2515

1.2510

1.2505

1.2500

-40 -30 -20 -10 0 10 20 30 40 50 60 70 90

TEMPERATURE (°C)

FIGURE 9. VTHPFI vs TEMPERATURE

ISL88705EVAL1 and Applications

The ISL88705EVAL1 supports all six of the ISL88705-

ISL88813 devices, enabling evaluation of basic functional

operation and common application implementations.

Figures 15 and 17 illustrate the ISL88705EVAL1 in

photographic and schematic forms respectively.

The ISL88705EVAL1 is divided into two banks; each bank

having one each of the three available pinouts. The top bank

is fully populated and immediately usable whereas the

bottom bank is unpopulated. Samples of other sample

variants can be evaluated singularly or in combination with

any other variant to provide a specific voltage monitoring

solution. The left position has a ISL88705IB846Z monitoring

the VDD rail voltage for a minimum of 4.64V with reset

signaling. In addition, the power fail input (PFI) is being

compared to the internal PFI voltage reference of 1.25V and

the power fail output (PFO) will report the PFI condition. This

feature can be used for monitoring an auxiliary voltage,

providing an early warning of a brownout or power failure or

presence detection in a system.

The middle position has the ISL88813IB846Z installed and is

set up as a 5V window detector with jumper J1 installed. The

VDD monitors for UV and the PFI for OV via the R3, R4

divider. The PFO output is inverted and connected to the

manual reset input (MR) via U4. Hence a reset signal is

generated when 4.64V < VDD > 5.38V. With J1 removed the

PFO will be an OV indicator but no reset signal will be

generated. Both of these positions share a common

Watchdog input (WDI) signal although each has its own

Watchdog output (WDO).

The right position has the ISL88707IB846Z and is set up as

a +12V and +5V UV monitor with reset signal. The PFI

allows monitoring of any voltage above the 1.25V PFI

reference and with a resistor divider this is used to monitor

the 12V. The ISL88707 and ISL88708 have the unique

feature of an adjustable time to reset (tPOR)signal

FN8092.3

December 6, 2006

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