IDT54FCT821ALSOB データシートの表示（PDF） - Integrated Device Technology
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IDT54FCT821ALSOB Datasheet PDF : 8 Pages
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IDT54/74FCT821/823/824/825A/B/C
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PRODUCT SELECTOR GUIDE
Non-inverting
Inverting
Device
10-Bit
9-Bit
8-Bit
54/74FCT821A/B/C 54/74FCT823A/B/C 54/74FCT825A/B/C
54/74FCT824A/B/C
2608 tbl 01
PIN DESCRIPTION
Name
DI
CLR
CP
YI , YI
I/O
Description
I
The D flip-flop data inputs.
I
For both inverting and non-inverting
registers, when the clear input is LOW
and OE is LOW, the QI outputs are
LOW. When the clear input is HIGH,
data can be entered into the register.
I
Clock Pulse for the Register; enters
data into the register on the LOW-to-
HIGH transition.
O
The register three-state outputs.
EN
I
Clock Enable. When the clock enable
is LOW, data on the D I input is
transferred to the QI output on the
LOW-to-HIGH clock transition. When
the clock enable is HIGH, the QI
outputs do not change state,
regardless of the data or clock input
transitions.
OE
I
Output Control. When the OE input is
HIGH, the Y I outputs are in the high
impedance state. When the OE input is
LOW, the TRUE register data is
present at the Y I outputs.
2608 tbl 10
FUNCTION TABLE(1)
IDT54/74FCT821/823/825
Inputs
Internal/
Outputs
OE
CLR
EN
DI
CP
QI
YI Function
H
H
L
L
↑
L
Z
High Z
H
H
L
H
↑
H
Z
H
L
X
X
X
L
Z
Clear
L
L
X
X
X
L
L
H
H
H
X
X NC Z
Hold
L
H
H
X
X NC NC
H
H
L
L
↑
L
Z
H
H
L
H
↑
H
Z
L
H
L
L
↑
L
L
L
H
L
H
↑
H
H
Load
NOTE:
2608 tbl 02
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-HIGH
Transition, Z = High Impedance
FUNCTION TABLE(1)
IDT54/74FCT824
Inputs
Internal/
Outputs
OE
CLR
EN
DI
CP
QI
YI Function
H
H
L
L
↑
H
Z
High Z
H
H
L
H
↑
L
Z
H
L
X
X
X
L
Z
L
L
X
X
X
L
L
Clear
H
H
H
X
L
H
H
X
X NC Z
X NC NC
Hold
H
H
L
L
↑
H
Z
H
H
L
H
↑
L
Z
L
H
L
L
↑
H
H
L
H
L
H
↑
L
L
Load
NOTE:
2608 tbl 03
1. H = HIGH, L = LOW, X = Don’t Care, NC = No Change, ↑ = LOW-to-
HIGH Transition, Z = High Impedance
7.19
3
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