SRK2000DTR(2012) データシートの表示（PDF） - STMicroelectronics

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SRK2000DTR
(Rev.:2012)

Synchronous rectifier smart driver for LLC resonant converters

STMicroelectronics 

Application information

SRK2000

erroneous decisions, the sleep-mode condition must be confirmed for 16 consecutive

switching cycles of the resonant converter (i.e. 16 consecutive cycles for each SR MOSFET

of the center-tap).

Once in sleep-mode, SR MOSFET gate driving is re-enabled when the conduction time of

the body diode (or the external diodes in parallel to the MOSFET) exceeds 60% (DON) of the

switching cycles. Also in this case the decision is made considering the measurement on 8

consecutive switching cycles (i.e. 8 consecutive cycles for each SR MOSFET of the center-

tap). Furthermore, after each sleep-mode entering/exiting transition, the timing is ignored for

a certain number of cycles, to let the resulting transient in the output current fade out; then

the time check is enabled. The number of ignored resonant converter switching cycles is

128 after entering sleep-mode and 256 after exiting sleep-mode.

5.5

Protection against current reversal

The IC provides protection against SR MOSFET current reversal. If a current reversal

condition is detected for two consecutive switching cycles, the IC goes into sleep-mode,

avoiding the turn-on of the SR MOSFETs until a safe condition is restored.

5.6

Layout guidelines

The IC is designed with two grounds, SGND and PGND.

SGND is used as the ground reference for all the internal high-precision analog blocks,

while PGND is the ground reference for all the noisy digital blocks, as well as the current

return for the gate drivers. In addition, it is also the ground for the ESD protection circuits.

SGND is protected by ESD events versus PGND through two anti-parallel diodes.

When laying out the PCB, make sure to keep the source terminals of both SR MOSFETs as

close as possible to one another and to route the trace that goes to PGND separately from

the load current return path. This trace should be as short as possible and be as close to the

physical source terminals as possible. A layout that is as geometrically symmetrical as

possible helps the circuit to operate in the most electrically symmetrical way as possible.

SGND should be directly connected to PGND using a path as short as possible (under the

device body).

Also drain voltage sensing should be performed as physically close to the drain terminals as

possible: any stray inductance crossed by the load current that is in the drain-to-source

voltage sensing circuit may significantly alter the current reading, leading to a premature

turn-off of the SR MOSFET. It is worth mentioning that, especially in higher power

applications or at higher operating frequencies, even the stray inductance of the internal

wire bonding can be detrimental. In this case, a cautious selection of the SR MOSFET

package is required.

The use of bypass capacitors between Vcc and both SGND and PGND is recommended.

They should be low-ESR, low-ESL types and located as close to the IC pins as possible.

Sometimes a series resistor (in the tens) between the converter's output voltage and the

Vcc pin, forming an RC filter along with the bypass capacitor, is useful in order to get a

cleaner Vcc voltage.

14/17

Doc ID 17811 Rev 2

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