PCA9559 データシートの表示（PDF） - NXP Semiconductors.

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PCA9559

5-bit multiplexed/1-bit latched 6-bit I2C EEPROM DIP switch

NXP Semiconductors. 

Philips Semiconductors

5-bit multiplexed/1-bit latched 6-bit

I2C EEPROM DIP switch

Product data

PCA9559

PIN CONFIGURATION

FEATURES

• 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch

• 6-bit internal non-volatile register

• Internal non-volatile register programmable and readable via

I2C-bus

• Override input forces all outputs to logic 0

• 5 open drain multiplexed outputs

• 1 open drain non-multiplexed (latched) output

• 5 V and 2.5 V tolerant inputs

• Useful for ‘jumperless’ configuration of PC motherboards

• 2 address pins, allowing up to 4 devices on the I2C-bus

• ESD protection exceeds 2000 V HBM per JESD22-A114,

200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101

• Latch-up testing is done to JESDEC Standard JESD78 which

exceeds 100 mA

DESCRIPTION

The PCA9559 is a 20-pin CMOS device consisting of one 6-bit

non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit

multiplexed output with one latched EEPROM bit. It is used for DIP

switch-free or jumper-less system configuration and supports Mobile

and Desktop VID Configuration, where 2 preset values (1 set of

internal non-volatile registers and 1 set of external hardware pins)

set processor voltage for operation in either performance or deep

sleep modes. The PCA9559 is also useful in server and

telecom/networking applications when used to replace DIP switches

or jumpers, since the settings can be easily changed via I2C/SMBus

without having to power down the equipment to open the cabinet.

The non-volatile memory retains the most current setting selected

before the power is turned off.

The PCA9559 typically resides between the CPU and Voltage

Regulator Module (VRM) when used for CPU VID (Voltage

IDentification code) configuration. It is used to bypass the

CPU-defined VID values and provide a different set of VID values to

the VRM, if an increase in the CPU voltage is desired. An increase

in CPU voltage combined with an increase in CPU frequency leads

to a performance boost of up to 7.5%. Lower CPU voltage reduces

power consumption.

The PCA9559 has 2 address pins allowing up to 4 devices to be

placed on the same I2C-bus or SMBus.

I2C SCL 1

I2C SDA 2

A1 3

A0 4

MUX_IN A 5

MUX_IN B 6

MUX_IN C 7

MUX_IN D 8

MUX_IN E 9

GND 10

20 VCC

19 WP

18 OVERRIDE_N

17 NON_MUXED_OUT

16 MUX_OUT A

15 MUX_OUT B

14 MUX_OUT C

13 MUX_OUT D

12 MUX_OUT E

11 MUX_SELECT

SW00216

Figure 1. Pin configuration

PIN DESCRIPTION

PIN

NUM-

BER

1

2

SYMBOL

I2C SCL

I2C SDA

3

A1 Address

4

A0 Address

5-9

MUX_IN A-E

10

GND

11

MUX_SELECT

12-16

17

18

19

20

MUX_OUT E-A

NON_MUXED_

OUT

OVERRIDE_N

WP

VCC

FUNCTION

Serial I2C-bus clock

Serial bi-directional I2C-bus data

A1

A0

External inputs to multiplexer

Ground

Selects MUX_IN inputs or register

contents for MUX_OUT outputs

Open drain multiplexed outputs

Open drain outputs from

non-volatile memory

Forces all outputs to logic 0

Non-volatile register write-protect

Power supply: +3.0 to +3.6 V

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

20-Pin Plastic TSSOP

0 to +70 °C

PCA9559PW

PCA9559

Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging.

DRAWING NUMBER

SOT360-1

2003 Jun 27

2

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