MACH211SP-10YC データシートの表示（PDF） - Lattice Semiconductor

部品番号

コンポーネント説明

メーカー

MACH211SP-10YC

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

Output Enable

Product Terms

(Common to bank of

I/O Cells)

01

11

VCC

10

00

From Output

Macrocell

To Switch

Matrix

To Buried

Macrocell

(MACH 2 only)

14051K-007

Figure 7. I/O Cell

SPEEDLOCKING FOR GUARANTEED FIXED TIMING

The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in

both raw speed, and even more importantly, guaranteed fixed speed. The design of the switch

matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required

by the design. Other non-Lattice/Vantis CPLDs incur serious timing delays as product terms expand

beyond their typical 4 or 5 product term limits (Figure 8). Speed and SpeedLocking combine to

give designers easy access to the performance required in today’s designs.

MACH 1 & 2 SpeedLocking

• Patented Architecture

• Path Independent

• Logic/Routing Independent

• Guaranteed Fixed Timing

• Up to 16 Product Terms per Output

Non-MACH

• Variable

• Path Dependent

• Logic/Routing Dependent Delays

• Unpredictable

• 4-5 Product Terms before Delays

SpeedLocking

11

10

tPD (ns)

9

8

7

6

5

Shared Expander Delay

10.4 ns

8.8 ns

Parallel Expander Delay

6.6 ns

5.8 ns

5 ns

Non-MACH

7.4 ns

MACH 1 & 2

5 PT

10 PT 15 PT

Product Terms

Figure 8. Timing in MACH 1 & 2 vs. Non-MACH Devices

14051K-001

12

MACH 1 & 2 Families

Share Link: