MACH211SP-10YC データシートの表示（PDF） - Lattice Semiconductor

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MACH211SP-10YC

High-Performance EE CMOS Programmable Logic

Lattice Semiconductor 

BLOCK DIAGRAM (MACH131, MACH131SP)

Block A

I/O0 – I/O15

Block B

I/O16 – I/O31

16

I/O Cells

4

16

16

Macrocells

OE

52 x 70

AND Logic Array

and

Logic Allocator

16

I/O Cells

4

16

16

4

Macrocells

OE

52 x 70

AND Logic Array

and

Logic Allocator

26

26

Switch Matrix

26

26

52 x 70

AND Logic Array

and

Logic Allocator

OE

Macrocells

4

16

16

I/O Cells

16

52 x 70

AND Logic Array

and

Logic Allocator

OE

4

Macrocells

4

16

16

I/O Cells

16

I2, I5

4

2

4

4

I/O48 – I/O63

Block D

I/O32 – I/O47

Block C

CLK0/I0, CLK1/I1

CLK2/I3, CLK3/I4

14051K-009

20

MACH 1 & 2 Families

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